HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 532

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 20 Power-Down Modes
20.4
20.4.1
A transition is made to software standby mode if the SLEEP instruction is executed when the
SBYCR SSBY bit is set to 1. In this mode, the CPU, on-chip supporting modules, and oscillator,
all stop. However, the contents of the CPU's internal registers, on-chip RAM data, and the states
of on-chip supporting modules other than the SCI, A/D converter, HCAN, and the states of I/O
ports, are retained. In this mode, the oscillator stops, and therefore power dissipation is
significantly reduced.
20.4.2
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ5), or by
means of the RES pin or STBY pin.
• Clearing with an interrupt:
• Clearing with the RES pin:
• Clearing with the STBY pin:
Rev. 7.00 Sep. 11, 2009 Page 496 of 566
REJ09B0211-0700
When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and
after the time set in bits STS0 to STS2 in SBYCR has elapsed, stable clocks are supplied to the
entire chip, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5
is generated. Software standby mode cannot be cleared if the interrupt has been masked on the
CPU side or has been designated as a DTC activation source.
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held low
until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception
handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Software Standby Mode
Transition to Software Standby Mode
Clearing Software Standby Mode