UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 444

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

442
(c) External trigger mode
Of the ANIn0 to ANIn3 pins, the analog input pin specified by the ADAnS.ADAnS1 and ADAnS.ADAnS0
bits is used for A/D conversion in this mode. The ADTRGn pin is used for the A/D conversion start timing.
The ADTRG0 pin alternates as the P04/INTP4 pin, and the ADTRG1 pin as the P05/INTP5 pin. To set the
external trigger mode, set the PMC04 and PMC05 bits of port mode control register 0 (PMC0) to 1, and
the ADAnM2.ADAnTMD1 bit to 0.
The valid edge of the external input signal in the external trigger mode can be selected from the rising
edge, falling edge, or both the rising and falling edges, according to the setting of the ADAnM0.ADAnETS1
and ADAnM0.ADAnETS0 bits.
When the ADAnM0.ADAnCE bit is set to 1, the A/D converter waits for a trigger and starts conversion
when the trigger is input from the ADTRGn pin.
After the end of conversion, the conversion result is stored in A/Dn conversion result register m
(ADAnCRm) and, at the same time, an A/Dn conversion end interrupt request signal (INTADn) is
generated.
If the operation mode set by the ADAnM0.ADAnMD1 and ADAnM0.ADAnMD0 bits is the continuous select
mode or continuous scan mode, the conversion operation is repeated, with the next ADTRGn signal as the
trigger, unless the ADAnM0.ADAnCE bit is cleared to 0. In the one-shot select mode or one-shot scan
mode, the A/D converter waits for a trigger.
When conversion is started, the ADAnM0.ADAnEF bit is set to 1 (conversion in progress). While the
converter waits for a trigger, however, the ADAnEF bit = 0 (conversion stopped).
If the valid trigger is input during A/D conversion, the conversion is stopped and is executed again from the
beginning.
conversion is stopped and the converter waits for a trigger again.
Caution In the external trigger mode, make sure that the ADTRGn signal (A/D conversion start
Remark
timing) is not generated at an interval shorter than the minimum number of conversion
clocks that can be specified by the ADAnM1.ADAnFR1 and ADAnM1.ADAnFR0 bits. If
the ADTRGn signal is generated at an interval shorter than the minimum number of
conversion clocks, the last trigger is valid.
n = 0, 1
m = 0 to 3
If the ADAnM0, ADAnM2, and ADAnS registers are written during A/D conversion, the
CHAPTER 11 A/D CONVERTERS 0 AND 1
User’s Manual U17716EJ2V0UD