UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 579

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.8 Interrupt Response Time of CPU
signals successively, input the next interrupt request signal at least 4 clocks after the preceding interrupt.
Except the following cases, the interrupt response time of the CPU is 4 clocks minimum. To input interrupt request
• In IDLE/STOP mode
• When interrupt request non-sampling instructions are successively executed (see 14.9 Periods in Which CPU
• When an on-chip peripheral I/O register is accessed
(1) Minimum interrupt response time
Note For interleave access, see 8.1.2
(2) Maximum interrupt response time
Remark
Note For details, see 14.4.1 (2) (a) External interrupt noise elimination control register (INTPNRC).
Does Not Acknowledge Interrupts.)
Maximum
Minimum
Instruction (first instruction of interrupt servicing routine)
Instruction (first instruction of interrupt servicing routine)
(U15943E).
Figure 14-13. Pipeline Operation at Interrupt Request Signal Acknowledgment (Outline)
INT1 to INT4: Interrupt acknowledgment processing
IFX:
IDX:
Interrupt response time (internal system clock)
interrupt
Internal
4
7
Interrupt acknowledgment operation
Interrupt acknowledgment operation
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Analog delay time
Analog delay time
Invalid instruction fetch
Invalid instruction decode
INTP0 to INTP5
4 +
7 +
Interrupt request
External interrupt
Interrupt request
Internal clock
Instruction 1
Instruction 2
Internal clock
Instruction 1
Instruction 2
User’s Manual U17716EJ2V0UD
Digital noise filter
Digital noise filter
2-clock branch in the V850ES Architecture User’s Manual
4 + Note +
7 + Note +
INTP6
IF
IF
IFX
IF
IFX
IF
The following cases are exceptions.
• In IDLE/STOP mode
• Two or more interrupt request non-sample instructions are
• Access to on-chip peripheral I/O register
INT1 INT2 INT3 INT3 INT3 INT3 INT4
IFX
ID
executed in succession
INT1 INT2 INT3 INT4
IFX
ID
4 system clocks
IDX
EX MEM MEM MEM MEM WB
IDX
EX
7 system clocks
DF
WB
Interleave access
Conditions
IF
IF
ID
Note
IF
EX
IF
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