UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 531

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SIB0 pin capture
INTCB0R signal
INTCB0T signal
(2) Operation timing
CB0TSF bit
SCKB0 pin
SOB0 pin
SIB0 pin
(1) Write 00H to the CB0CTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CB0CTL2 register, and set the transfer data length to 8 bits.
(3) Write E3H to the CB0CTL0 register, and select the transmission/reception mode, MSB first, and
(4) The CB0STR.CB0TSF bit is set to 1 by writing the transmit data to the CB0TX register, and
(5) When transmission/reception is started, output the serial clock to the SCKB0 pin, output the transmit
(6) When transfer of the transmit data from the CB0TX register to the shift register is completed and
(7) To continue transmission/reception, write the transmit data to the CB0TX register again after the
(8) When one transmission/reception is completed, the reception end interrupt request signal (INTCB0R)
(9) When a new transmit data is written to the CB0TX register before communication completion, the next
(10) Read the CB0RX register.
timing
f
continuous transfer mode at the same time as enabling the operation of the communication clock
(f
transmission/reception is started.
data to the SOB0 pin in synchronization with the serial clock, and capture the receive data of the SIB0
pin.
writing to the CB0TX register is enabled, the transmission enable interrupt request signal (INTCB0T) is
generated.
INTCB0T signal is generated.
is generated, and reading of the CB0RX register is enabled.
communication is started following communication completion.
XX
CCLK
/2, and master mode.
(1)
(2)
(3)
).
(4)
(5)
Bit 7
Bit 7
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
(6)
Bit 6
Bit 6
Bit 5 Bit 4 Bit 3
Bit 5 Bit 4 Bit 3
(7)
User’s Manual U17716EJ2V0UD
Bit 2
Bit 2
Bit 1
Bit 1
(8) (9) (10) (11)
Bit 0
Bit 0 Bit 7
Bit 7
Bit 6
Bit 6
Bit 5 Bit 4 Bit 3
Bit 5 Bit 4 Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
(12)
Bit 0
Bit 0
(13) (15)
CCLK
) =
(1/2)
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