UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 577

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UPD70F3713GC-8BS-A

Manufacturer Part Number
UPD70F3713GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet

Specifications of UPD70F3713GC-8BS-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3713GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14.7 Multiple Interrupt Servicing Control
interrupted during servicing if there is an interrupt request signal with a higher priority level, and the higher priority
interrupt request signal is acknowledged and serviced first.
that interrupt request signal is held pending.
Thus, to execute multiple interrupts, it is necessary to set the interrupt enabled state (PSW.ID bit = 0) even in an
interrupt servicing routine.
exception servicing program, it is necessary to save EIPC and EIPSW.
Multiple interrupt servicing control is a process by which an interrupt request that is currently being serviced can be
If there is an interrupt request signal with a lower priority level than the interrupt request currently being serviced,
Multiple interrupt servicing control of maskable interrupts is executed when interrupts are enabled (PSW.ID bit = 0).
If maskable interrupts are enabled or a software exception is generated in a maskable interrupt or software
This is accomplished by the following procedure.
(1) Acknowledgment of maskable interrupt signals in servicing program
Service program of maskable interrupt or exception
• EIPC saved to memory or register
• EIPSW saved to memory or register
• EI instruction (interrupt acknowledgment enabled)
• DI instruction (interrupt acknowledgment disabled)
• Saved value restored to EIPSW
• Saved value restored to EIPC
• RETI instruction
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CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User’s Manual U17716EJ2V0UD
← Maskable interrupt acknowledgment
575

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