UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 598

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UPD70F3713GC-8BS-A

Manufacturer Part Number
UPD70F3713GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet

Specifications of UPD70F3713GC-8BS-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number:
UPD70F3713GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
<R>
596
(3) Control registers
(a) Low-voltage detection register (LVIM)
Note This register is cleared to 00H after a reset by RESET pin input, power-on-clear circuit (POC),
The LVIM register is used to enable or disable low voltage detection, and to set the operation mode of the
low-voltage detector. The LVIM register is a special register. It can be written only by a combination of
specific sequences (see 3.4.7 Special registers).
This register can be read or written in 8-bit or 1-bit units. However, bit 0 is read-only.
This register is cleared to 00H by a reset via RESET pin input, power-on-clear circuit (POC), and watchdog
timer overflow. This register is set to 82H after a reset by the low-voltage detector (LVI).
Cautions 1. After setting the LVION bit to 1, wait for 0.1 ms (TYP) (target value) before checking
After reset: 00H
LVIM
and watchdog timer overflow. This register is set to 82H after a reset by the low-voltage detector
(LVI).
2. The value of the LVIF flag is output as the output signal INTLVI when the LVION bit
3. Be sure to clear bits 2 to 6 to “0”.
4. When writing to the LVIM register, use command register PRCMD2.
LVION
LVION
LVIMD
LVIF
<7>
0
1
0
1
0
1
the voltage using the LVIF bit.
= 1 and LVIMD bit = 0.
Note
Disable operation.
Enable operation.
Generate interrupt request signal INTLVI when supply voltage < detection
voltage.
Generate internal reset signal LVIRES when supply voltage < detection voltage.
When supply voltage > detection voltage, or when operation is disabled
Supply voltage < detection voltage
R/W
6
0
CHAPTER 16 RESET FUNCTIONS
Address: FFFFF890H
Selection of operation mode of low voltage detection
User’s Manual U17716EJ2V0UD
Low voltage detection operation enable or disable
5
0
Low voltage detection flag
4
0
3
0
2
0
LVIMD
<1>
LVIF
<0>

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