UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 672

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Modification of description in 6.6.5 (2) (b) 0%/100% output of PWM waveform
Modification of description in Figure 6-41 Configuration in Pulse Width Measurement Mode
Modification of description in 6.6.7 Pulse width measurement mode (TPkMD2 to TPkMD0 bits = 110)
Modification of description in Figure 6-43 Register Setting in Pulse Width Measurement Mode
Deletion of description from Figure 6-44 Software Processing Flow in Pulse Width Measurement Mode
Addition of description to Table 7-1 TMQn Overview
Modification of description in 7.4 (3) TMQn I/O control register 0 (TQnIOC0)
Modification of description in 7.6 (1) (a) Counter start operation
Modification of description in Figure 7-10 Register Setting for Interval Timer Mode Operation
Addition of description to Figure 7-11 Software Processing Flow in Interval Timer Mode
Modification of description in 7.6.1 (2) (d) Operation of TQnCCR1 to TQnCCR3 registers
Addition of 7.6.1 (3) Operation by external event count input (EVTQ0)
Addition of description to 7.6.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001)
Addition of description to Figure 7-17 Register Setting for Operation in External Event Count Mode
Addition of description to 7.6.2 (2) Operation timing in external event count mode
Modification of figure description in Figure 7-23 Basic Timing in External Trigger Pulse Output Mode
Addition of description to 7.6.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010)
Modification of description in 7.6.3 (2) (b) 0%/100% output of PWM waveform
Modification of description in Figure 7-28 Register Setting in One-Shot Pulse Output Mode
Modification of description in Figure 7-29 Software Processing Flow in One-Shot Pulse Output Mode
Modification of description in 7.6.5 (2) (b) 0%/100% output of PWM waveform
Modification of description in 7.6.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110)
Addition of description to 9.2 (1) TMQ1 dead-time compare register (TQ1DTC)
Addition of description to 9.3 (2) TMQ1 option register 1 (TQ1OPT1)
Addition of description to 9.3 (3) TMQ1 option register 2 (TQ1OPT2)
Addition of description to Figure 9-3 Output Control of TOQ1Tm and TOQ1Bm Pins (Without Dead Time)
Modification of Figure 9-5 Outline of 6-Phase PWM Output Mode
Modification of Figure 9-9 0% PWM Output Waveform (with Dead Time)
Modification of Figure 9-10 100% PWM Output Waveform (with Dead Time)
Modification of Figure 9-11 PWM Output Waveform from 0% to 100% and from 100% to 0% (with Dead
Time)
Addition of description to 9.4.3 Interrupt culling function
Modification of description in 11.4.1 Basic operation
Modification of Figure 12-1 Block Diagram of UARTAn
Modification of description in 12.2 (5) UARTAn status register (UAnSTR)
Modification of description in 12.3 (1) UARTAn control register 0 (UAnCTL0)
Modification of Figure 12-5 Continuous Transmission Operation Timing
Modification of figure description in 13.4.7 (2) Operation timing
Addition of description to 14.3.4 Interrupt control registers (xxICn)
Addition of description to 14.6.1 (2) Restore
APPENDIX D REVISION HISTORY
User’s Manual U17716EJ2V0UD
Description
(2/3)