UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 670

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UPD70F3713GC-8BS-A

Manufacturer Part Number
UPD70F3713GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet

Specifications of UPD70F3713GC-8BS-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3713GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
668
Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the
13. i i i i i : Lower 5 bits of imm9.
14. Do not specify the same register for general-purpose registers reg1 and reg3.
15. sp/imm: specified by bits 19 and 20 of the sub-opcode.
16. ff = 00: Load sp in ep.
17. If imm = imm32, n + 3 clocks.
18. r r r r r : Other than 00000.
19. ddddddd: Higher 7 bits of disp8.
20. dddd: Higher 4 bits of disp5.
21. dddddd: Higher 6 bits of disp8.
22. Do not make a register combination that satisfies all the following conditions when executing the “MUL
reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic
description and in the opcode differs from other instructions.
r r r r r
RRRRR = reg2 specification
I I I I : Higher 4 bits of imm9.
reg1, reg2, reg3” and “MULU reg1, reg2, reg3” instructions. If an instruction that satisfies these
conditions is executed, the operation is not guaranteed.
• reg1 = reg3
• reg1 ≠ reg2
• reg1 ≠ r0
• reg3 ≠ r0
01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep.
10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep.
11: Load 32-bit immediate data (bits 63 to 32) in ep.
= regID specification
APPENDIX C INSTRUCTION SET LIST
User’s Manual U17716EJ2V0UD

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