UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 521

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SIB0 pin capture
INTCB0R signal
(2) Operation timing
CB0TSF bit
SCKB0 pin
SIB0 pin
(1) Write 07H to the CB0CTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CB0CTL2 register, and set the transfer data length to 8 bits.
(3) Write A1H to the CB0CTL0 register, and select the reception mode and MSB first at the same time as
(4) The CB0STR.CB0TSF bit is set to 1 by performing a dummy read of the CB0RX register, and the
(5) When a serial clock is input, capture the receive data of the SIB0 pin in synchronization with the serial
(6) When reception of the transfer data length set with the CB0CTL2 register is completed, stop the serial
(7) To continue reception, read the CB0RX register with the CB0CTL0.CB0SCE bit = 1 remained after the
(8) To end reception, write the CB0SCE bit = 0.
(9) Read the CB0RX register.
(10) To end reception, write the CB0CTL0.CB0PWR bit = 0 and the CB0CTL0.CB0RXE bit = 0.
timing
external clock (SCKB0), and slave mode.
enabling the operation of the communication clock (f
device waits for a serial clock input.
clock.
clock output and data capturing, generate the reception end interrupt request signal (INTCB0R) at the
last edge of the serial clock, and clear the CB0TSF bit to 0.
INTCB0R signal is generated, and wait for a serial clock input.
(1)
(2)
(3)
(4)
(5)
Bit 7
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
User’s Manual U17716EJ2V0UD
Bit 1
(6)
Bit 0
(7)
CCLK
Bit 7
).
Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
(8)
(9)
(10)
CCLK
) =
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