UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 459

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.6 Operation in Timer Trigger Mode
(TQTADT1n) from the timer (motor control function) (see Figure 11-2).
the TQ1AT10 to TQ1AT13 bits of TMQ1 option register 3 (TQ1OPT3). The trigger sources of the motor control
function that can be selected as the A/D conversion start trigger, which is a timer trigger, are the INTTP1CC0,
INTTP1CC1, INTTQ1CC0, and INTTQ1OV signals (two or more signals can be selected).
trigger signal (TQTADT1n) selected for the motor control function.
trigger signal is input, it starts A/D conversion.
and, at the same time, the A/Dn conversion end interrupt request signal (INTADn) is generated.
ADAnM0.ADAnMD1 and ADAnM0.ADAnMD0 bits.
converter is waiting for a trigger, the ADAnM0.ADAnEF bit = 0 (conversion stopped).
beginning. If the ADAnM0, ADAnM2, and ADAnS registers are written during A/D conversion, the conversion is
stopped and the A/D converter waits for a trigger again.
With A/D converter n, the conversion timing is specified by using the A/D conversion start trigger signal
• Timer trigger of A/D converter 0: TQTADT10
• Timer trigger of A/D converter 1: TQTADT11
The TQTADT1n signal is set by using the TQ1AT00 to TQ1AT03 bits of TMQ1 option register 2 (TQ1OPT2) and
When the ADAnM2.ADAnTMD1 bit is set 1, A/D conversion is started at the rising edge of the A/D conversion start
When the ADAnM0.ADAnCE bit is set to 1, the A/D converter waits for a trigger and, when the A/D conversion start
After the end of A/D conversion, the conversion result is stored in A/Dn conversion result register m (ADAnCRm)
After the end of A/D conversion, the A/D converter waits for a trigger regardless of the operation mode set by the
When conversion is started, the ADAnM0.ADAnEF bit is set to 1 (conversion in progress). However, while the A/D
If a valid trigger is input during A/D conversion, the conversion operation is stopped and started again from the
Caution In timer trigger mode, make sure that the A/D conversion start trigger signal (A/D conversions
Remark
start timing) is not generated at an interval shorter than the minimum number of conversion
clocks that can be specified by the ADAnM1.ADAnFR1 and ADAnM1.ADAnFR0 bits. If the A/D
conversion start trigger signal is generated at an interval shorter than the minimum number of
conversion clocks, the last trigger is valid.
n = 0, 1
m = 0 to 3
CHAPTER 11 A/D CONVERTERS 0 AND 1
User’s Manual U17716EJ2V0UD
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