UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 617

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
<R>
<R>
<R>
<R>
<R>
the V850ES/IE2. For details, refer to the PG-FP4 User’s Manual (U15260E) and PG-FP5 User’s Manual (U18865E).
FLMD0
FLMD1
VDD
GND
CLK
RESET
SI/RxD
SO/TxD
SCK
HS
Signal Name
(3) CSIB0 + HS
The dedicated flash memory programmer outputs the transfer clock, and the V850ES/IE2 operates as a slave.
When the PG-FP4 or PG-FP5 is used as the dedicated flash memory programmer, it sends the following signals to
Notes 1. Wire these pins as shown in Figure 18-6, or connect them to GND via a pull-down resistor on board.
Remark
Note Connect the FLMD1 pin to the flash memory programmer or connect to a GND via a pull-down resistor
Note 3
Serial clock: 2.4 kHz to 2.5 MHz (MSB first)
Table 18-5. Signal Connections of Dedicated Flash Memory Programmer (PG-FP4 and PG-FP5)
2. Connect this pin when power is supplied from PG-FP4 and PG-FP5.
3. In the V850ES/IE2, external clock input is prohibited. Create an oscillator on board and supply the clock
on the board.
Figure 18-5. Communication with Dedicated Flash Memory Programmer (CSIB0 + HS)
It does not have to be connected if an on-board power supply is used.
via that oscillator.
×: Does not have to be connected.
Output
Output
Output
Output
Input
Output
Output
Input
: Must be connected.
I/O
memory programmer
−
−
Dedicated flash
PG-FP4 and PG-FP5
Write enable/disable
Write enable/disable
V
Ground
Reset signal
Receive signal
Transmit signal
Transfer clock
Handshake signal for CSIB0 + HS
communication
DD
voltage generation/voltage monitor
Pin Function
RESET
FLMD0
FLMD1
GND
SCK
−
CHAPTER 18 FLASH MEMORY
V
SO
HS
SI
DD
User’s Manual U17716EJ2V0UD
FLMD0
FLMD1
V
V
X1
RESET
SOB0/TXDA0
SIB0/RXDA0
SCKB0
P43
FLMD0
FLMD1
V
RESET
SOB0
SIB0
SCKB0
P43
V
DD
SS
V850ES/IE2
SS
DD
Note 3
Pin Name
, EV
, X2
Note
DD
Note 3
UARTA0
−
×
×
Note 1
Note 2
V850ES/IE2
Processing for Connection
CSIB0
Note 1
Note 2
−
×
CSIB0 + HS
Note 1
Note 2
−
615