HD64F2319VTE25 Renesas Electronics America, HD64F2319VTE25 Datasheet - Page 1049

• Manufacturer Part Number: HD64F2319VTE25
• Description: IC H8S MCU FLASH 512K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2319VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

SCR0—Serial Control Register 0
Bit
Initial value
Read/Write
Note: * TXI interrupt requests can be cleared by reading 1 from the
Transmit Interrupt Enable
0
1
Transmit-data-empty interrupt (TXI) request disabled *
Transmit-data-empty interrupt (TXI) request enabled
TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0.
:
:
:
R/W
TIE
7
0
Note: * RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF, FER, PER, or
Receive Interrupt Enable
0
1
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled *
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled
ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0.
R/W
RIE
Transmit Enable
Notes: 1. The TDRE flag in SSR is fixed at 1.
6
0
0
1
Transmission disabled *
Transmission enabled *
2. In this state, serial transmission is started when transmit data is written to TDR and the
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states.
Receive Enable
TDRE flag in SSR is cleared to 0.
SMR setting must be performed to decide the transmit format before setting the TE bit to 1.
R/W
TE
0
1
5
0
Reception disabled *
Reception enabled *
2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock
input is detected in synchronous mode.
SMR setting must be performed to decide the receive format before setting the RE bit to 1.
R/W
RE
Multiprocessor Interrupt Enable
Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR,
4
0
0
1
2
1
Multiprocessor interrupts disabled
[Clearing conditions]
· When the MPIE bit is cleared to 0
· When data with MPB = 1 is received
Multiprocessor interrupts enabled *
Receive-data-full interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting
of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit
set to 1 is received
receive error detection, and setting of the RDRF, FER, and ORER flags in SSR, is not
performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1,
the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when
the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled.
MPIE
R/W
2
3
0
1
Note: * TEI clearing can be performed by reading 1 from the TDRE flag in SSR, then
Transmit End Interrupt Enable
0
1
Transmit-end interrupt (TEI) request disabled *
Transmit-end interrupt (TEI) request enabled *
clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0.
TEIE
R/W
2
0
Rev.7.00 Feb. 14, 2007 page 1015 of 1108
Notes: 1. Outputs a clock of the same frequency as the bit rate.
Clock Enable
CKE1
0
1
R/W
1
0
0
1
0
1
2. Inputs a clock with a frequency 16 times the bit rate.
H'FF7A
Asynchronous
mode
Synchronous
mode
Asynchronous
mode
Synchronous
mode
Asynchronous
mode
Synchronous
mode
Asynchronous
mode
Synchronous
mode
Appendix B Internal I/O Registers
CKE0
R/W
0
0
Internal clock/SCK pin functions
as I/O port
Internal clock/SCK pin functions
as serial clock output
Internal clock/SCK pin functions
as clock output *
Internal clock/SCK pin functions
as serial clock output
External clock/SCK pin functions
as clock input *
External clock/SCK pin functions
as serial clock input
External clock/SCK pin functions
as clock input *
External clock/SCK pin functions
as serial clock input
REJ09B0089-0700
2
2
1
SCI0