HD64F2319VTE25 Renesas Electronics America, HD64F2319VTE25 Datasheet - Page 25

• Manufacturer Part Number: HD64F2319VTE25
• Description: IC H8S MCU FLASH 512K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2319VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 11 Watchdog Timer ..............................................................................415
11.1 Overview........................................................................................................................... 415
11.2 Register Descriptions ........................................................................................................ 418
11.3 Operation........................................................................................................................... 423
11.4 Interrupts ........................................................................................................................... 428
11.5 Usage Notes ...................................................................................................................... 428
Section 12 Serial Communication Interface (SCI) ............................................431
12.1 Overview........................................................................................................................... 431
12.2 Register Descriptions ........................................................................................................ 436
10.6.3 Contention between TCOR Write and Compare Match ...................................... 410
10.6.4 Contention between Compare Matches A and B ................................................. 411
10.6.5 Switching of Internal Clocks and TCNT Operation............................................. 411
10.6.6 Interrupts and Module Stop Mode ....................................................................... 413
11.1.1 Features................................................................................................................ 415
11.1.2 Block Diagram ..................................................................................................... 416
11.1.3 Pin Configuration................................................................................................. 417
11.1.4 Register Configuration......................................................................................... 417
11.2.1 Timer Counter (TCNT)........................................................................................ 418
11.2.2 Timer Control/Status Register (TCSR) ................................................................ 419
11.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 421
11.2.4 Notes on Register Access..................................................................................... 422
11.3.1 Operation in Watchdog Timer Mode ................................................................... 423
11.3.2 Operation in Interval Timer Mode ....................................................................... 425
11.3.3 Timing of Overflow Flag (OVF) Setting ............................................................. 426
11.3.4 Timing of Watchdog Timer Overflow Flag (WOVF) Setting.............................. 427
11.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 428
11.5.2 Changing Value of CKS2 to CKS0...................................................................... 429
11.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 429
11.5.4 System Reset by WDTOVF Signal...................................................................... 429
11.5.5 Internal Reset in Watchdog Timer Mode............................................................. 430
12.1.1 Features................................................................................................................ 431
12.1.2 Block Diagram ..................................................................................................... 433
12.1.3 Pin Configuration................................................................................................. 434
12.1.4 Register Configuration......................................................................................... 435
12.2.1 Receive Shift Register (RSR) .............................................................................. 436
12.2.2 Receive Data Register (RDR) .............................................................................. 436
12.2.3 Transmit Shift Register (TSR) ............................................................................. 437
12.2.4 Transmit Data Register (TDR)............................................................................. 437
Rev.7.00 Feb. 14, 2007 page xxiii of xxxii
REJ09B0089-0700