HD64F2319VTE25 Renesas Electronics America, HD64F2319VTE25 Datasheet - Page 21

• Manufacturer Part Number: HD64F2319VTE25
• Description: IC H8S MCU FLASH 512K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2319VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.7
6.8
6.9
Section 7 Data Transfer Controller ....................................................................183
7.1
7.2
7.3
6.6.2
Bus Release....................................................................................................................... 177
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
Bus Arbitration.................................................................................................................. 180
6.8.1
6.8.2
6.8.3
6.8.4
Resets and the Bus Controller ........................................................................................... 181
Overview........................................................................................................................... 183
7.1.1
7.1.2
7.1.3
Register Descriptions ........................................................................................................ 186
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
Operation........................................................................................................................... 193
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10 Number of DTC Execution States ....................................................................... 208
Pin States in Idle Cycle ........................................................................................ 176
Overview.............................................................................................................. 177
Operation ............................................................................................................. 177
Pin States in External Bus Released State............................................................ 178
Transition Timing ................................................................................................ 179
Usage Note........................................................................................................... 180
Overview.............................................................................................................. 180
Operation ............................................................................................................. 180
Bus Transfer Timing ............................................................................................ 181
External Bus Release Usage Note........................................................................ 181
Features................................................................................................................ 183
Block Diagram ..................................................................................................... 184
Register Configuration......................................................................................... 185
DTC Mode Register A (MRA) ............................................................................ 186
DTC Mode Register B (MRB)............................................................................. 187
DTC Source Address Register (SAR).................................................................. 189
DTC Destination Address Register (DAR).......................................................... 189
DTC Transfer Count Register A (CRA) .............................................................. 189
DTC Transfer Count Register B (CRB)............................................................... 190
DTC Enable Registers (DTCER) ......................................................................... 190
DTC Vector Register (DTVECR)........................................................................ 191
Module Stop Control Register (MSTPCR) .......................................................... 192
Overview.............................................................................................................. 193
Activation Sources ............................................................................................... 197
DTC Vector Table................................................................................................ 198
Location of Register Information in Address Space ............................................ 201
Normal Mode....................................................................................................... 202
Repeat Mode ........................................................................................................ 203
Block Transfer Mode ........................................................................................... 204
Chain Transfer ..................................................................................................... 206
Operation Timing................................................................................................. 207
Rev.7.00 Feb. 14, 2007 page xix of xxxii
REJ09B0089-0700