AT89LP52-20MU Atmel, AT89LP52-20MU Datasheet - Page 24

• Manufacturer Part Number: AT89LP52-20MU
• Description: IC MCU 8051 8K FLASH SPI 44VQFN
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP52-20MU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VFQFN Exposed Pad
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: Serial
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5. Enhanced CPU
5.1
24
Fast Mode
AT89LP51/52 - Preliminary
The AT89LP51/52 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of standard
8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in performance is
due to two factors. First, the CPU fetches one instruction byte from the code memory every clock
cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute instructions in
parallel. This basic pipelining concept allows the CPU to obtain up to 1 MIPS per MHz. The
AT89LP51/52 also has a Compatibility mode that preserves the 12-clock machine cycle of stan-
dard 8051s like the AT89S51/52.
Fast (Single-Cycle) mode must be enabled by clearing the Compatibility User Fuse. (See
Configuration Fuses” on page
clock cycle. The 8051 instruction set allows for instructions of variable length from 1 to 3 bytes.
In a single-clock-per-byte-fetch system this means each instruction takes at least as many
clocks as it has bytes to execute. The majority of instructions in the AT89LP51/52 follow this
rule: the instruction execution time in system clock cycles equals the number of bytes per
instruction, with a few exceptions. Branches and Calls require an additional cycle to compute the
target address and some other complex instructions require multiple cycles.
Summary” on page 75.
Example of Fast mode instructions are shown in
take three times as long to execute if they are fetched from external program memory.
Figure 5-1.
Instruction Execution Sequences in Fast Mode
for more detailed information on individual instructions.
(A) 1-byte, 1-cycle instruction, e.g. INC A
(B) 2-byte, 2-cycle instruction, e.g. ADD A, #data
(C) 1-byte, 2-cycle instruction, e.g. INC DPTR
(D) MOVX (1-byte, 4-cycle)
CLK
86.) In this mode one instruction byte is fetched every system
S1
S1
S1
S1
ACCESS EXTERNAL
ADDR
READ OPERAND
READ NEXT
OPCODE
S2
S2
S2
MEMORY
READ NEXT OPCODE
READ NEXT OPCODE
S3
Figure
DATA
S4
5-1. Note that Fast mode instructions
READ NEXT
OPCODE
See “Instruction Set
3709B–MICRO–12/10
“User