AT89LP52-20MU Atmel, AT89LP52-20MU Datasheet - Page 34

• Manufacturer Part Number: AT89LP52-20MU
• Description: IC MCU 8051 8K FLASH SPI 44VQFN
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP52-20MU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VFQFN Exposed Pad
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: Serial
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Table 8-1.
8.2
34
Symbol
SMOD1
SMOD0
PWDEX
POF
GF1, GF0
PD
IDL
PCON = 87H
Not Bit Addressable
Bit
Power-down Mode
AT89LP51/52 - Preliminary
Function
Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.
Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after
a frame error regardless of the state of SMOD0.
Power-down Exit Mode. When PWDEX = 0, wake up from Power-down is externally controlled. When PWDEX = 1, wake
up from Power-down is internally timed.
Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not
affected by RST or BOD (i.e. warm resets).
General-purpose Flags
Power-down bit. Setting this bit activates power-down operation. The PD bit is cleared automatically by hardware when
waking up from power-down.
Idle Mode bit. Setting this bit activates Idle mode operation. The IDL bit is cleared automatically by hardware when
waking up from idle
PCON
SMOD1
7
– Power Control Register
CPU when an interrupt is generated. The timer and UART peripherals continue to function dur-
ing Idle. If these functions are not needed during idle, they should be explicitly disabled by
clearing the appropriate control bits in their respective SFRs. The watchdog may be selectively
enabled or disabled during Idle by setting/clearing the WDIDLE bit. The Brown-out Detector is
always active during Idle. Any enabled interrupt source or reset may terminate Idle mode. When
exiting Idle mode with an interrupt, the interrupt will immediately be serviced, and following RETI
the next instruction to be executed will be the one following the instruction that put the device
into Idle.
The power consumption during Idle mode can be further reduced by prescaling down the system
clock using the System Clock Divider
will affect all peripheral functions and baud rates may need to be adjusted to maintain their rate
with the new clock frequency.
.
Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops
the oscillator, disables the BOD and powers down the Flash memory in order to minimize power
consumption. Only the power-on circuitry will continue to draw power during Power-down. Dur-
ing Power-down, the power supply voltage may be reduced to the RAM keep-alive voltage. The
RAM contents will be retained, but the SFR contents are not guaranteed once V
reduced. Power-down may be exited by external reset, power-on reset, or certain enabled
interrupts.
SMOD0
6
PWDEX
5
POF
4
(Section 6.4 on page
GF1
3
GF0
2
30). Be aware that the clock divider
Reset Value = 000X 0000B
PD
1
3709B–MICRO–12/10
IDL
0
DD
has been