AT89LP52-20MU Atmel, AT89LP52-20MU Datasheet - Page 45

• Manufacturer Part Number: AT89LP52-20MU
• Description: IC MCU 8051 8K FLASH SPI 44VQFN
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP52-20MU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VFQFN Exposed Pad
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: Serial
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

11. Timer 0 and Timer 1
3709B–MICRO–12/10
The AT89LP51/52 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the following
features:
Timer 0 and Timer 1 have similar modes of operation. As timers, the timer registers normally
increase every clock cycle. Thus, the registers count clock cycles. The timer rate can be pres-
caled by a value between 1 and 16 using the Timer Prescaler (see
Timers share the same prescaler. In Compatibility mode CDV defaults to 2, so a clock cycle con-
sists of two oscillator periods,and the prescaler defaults to 6 making the count rate equal to 1/12
of the oscillator frequency. By default in Fast mode CDV = 0 and TPS = 0 so the count rate is
equal to the oscillator frequency.
As counters, the timer registers are incremented in response to a 1-to-0 transition at the corre-
sponding input pins, T0 or T1. In Fast mode the external input is sampled every clock cycle.
When the samples show a high in one cycle and a low in the next cycle, the count is incre-
mented. The new count value appears in the register during the cycle following the one in which
the transition was detected. Since 2 clock cycles are required to recognize a 1-to-0 transition,
the maximum count rate is 1/2 of the system frequency. There are no restrictions on the duty
cycle of the input signal, but it should be held for at least one full clock cycle to ensure that a
given level is sampled at least once before it changes.
In Compatibility mode the counter input sampling is controlled by the prescaler. Since TPS
defaults to 6 in this mode, the pins are sampled every six system clocks. Therefore the input sig-
nal should be held for at least six clock cycles to ensure that a given level is sampled at least
once before it changes.
Furthermore, the Timer or Counter functions for Timer 0 and Timer 1 have four operating modes:
13-bit timer, 16-bit timer, 8-bit auto-reload timer, and split timer. The control bits C/T in the Spe-
cial Function Register TMOD select the Timer or Counter function. The bit pairs (M1, M0) in
TMOD select the operating modes.
Table 11-1.
Name
TCON
TMOD
TL0
TL1
TH0
TH1
TCONB
• Two independent 16-bit timer/counters with 8-bit reload registers
• UART baud rate generation using Timer 1
• Output pin toggle on timer overflow
• Split timer mode allows for three separate timers (2 8-bit, 1 16-bit)
• Gated modes allow timers to run/halt based on an external input
Address
Timer 0/1 Register Summary
8CH
8DH
88H
89H
8AH
8BH
91H
Purpose
Control
Mode
Timer 0 low-byte
Timer 1 low-byte
Timer 0 high-byte
Timer 1 high-byte
Mode
AT89LP51/52 - Preliminary
Table 6-2 on page
Bit-Addressable
Y
N
N
N
N
N
N
30). Both
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