WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 10

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10
January 2008
November 2007
October 2007
August 2007
July 2007
June 2007
Date
1.5
1.1
1.0
0.7
0.6
0.5
Revision
Description
Initial release (Intel Confidential).
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Changed section 10.2.2.2 bit 31 assignment from 1b to 0b.
Changed word 0x0F bit 7 bit assignment (1b to 0b).
Added new Section 14 “Thermal Design Considerations”.
Updated MNG Mode description (loads from NVM work 0xF instead of word 10.
Updated the 82574L Resets table.
Added note “The 82574L requests I/O resources to support pre-boot operation (prior to the allocation of physical
memory base addresses”.
Updated CAP Offset 0xE4 bit 15 description.
Updated default values for Uncorrectable Error Severity and Correctable Error Mask registers.
Updated Figure 52.
Updated VALUE1 and VALUE2 byte numbers in Section 10.2.8.19.
Changed crystal drive level to 300 W.
Changed all 1.0 V dc references to 1.05 V dc.
Changed all 1.8 V dc references to 1.9 V dc.
Deleted “Default value of 0x5F20 and 0x5F28 are loaded from the NVM at power up" from the FFLT register description.
Added a note for EITR that in 10/100 Mb/s mode, the interval time is multiplied by four.
Updated the type and internal/external PU/PD for NC-SI pins.
Updated the NVMT pinout description.
Updated MNG_Mode to be loaded from NVM word 0x0F (instead of NVM word 0x10).
Updated default values for Uncorrectable Error Severity and Correctable Error Mask registers.
Updated section 9.1.6.1.7. Where applicable, changed milliseconds to micro seconds (bits 14:12 and 17:15).
Removed WUPL register information.
Noted that manageability can be supported with a 32 Kb EEPROM.
Updated NVMT symbol description in Section 2.3.4, Table 10.
Updated Sections 2, 3, 4, 5, 9, 12, and 13; as indicated by the change bars in the left margin.
Updated Sections 2, 3, 5, 6, 8, 10, and 12.
Added Sections 13, 14, 15, and 16.
Added Section 12.0 “Electrical Specifications”.
Updated Section 2.0 “Pin Interface”.
82574 GbE Controller—Datasheet