WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 109

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Non-Volatile Memory (NVM) Map—82574 GbE Controller
6.1.1.14
6.1.1.15
15
14:12
11:9
8:6
5:3
2:0
15
14
13
12
11:8
7:0
Bit
Bit
Reserved
L1_Act_Ext_Latency
L1_Act_Acc_Latency
L0s_Acc_Latency
L0s_Se_Ext_Latency
L0s_Co_Ext_Latency
DLLP timer enable
Reserved
Reserved
SER_EN
ExtraNFTS
NFTS
Name
Name
PCIe Init Configuration 1 Word (Word 0x18)
PCIe Init Configuration 2 Word (Word 0x19)
0b
0b
1b
0b
0x1
0x50
0b
0x6 (32 s-64 s)
0x6 (32 s-64 s)
0x3 (512 ns)
0x1
0x1
Hardware
Hardware
Default
Default
0b
0x6 (32 s-64 s)
0x6 (32 s-64 s)
0x3 (512 ns)
0x1
0b
0b
1b
1b
0x1
0x50
0x1
NVM Image
NVM Image
Setting
Setting
Reserved
L1 active exit latency for the configuration
space.
L1 active acceptable latency for the
configuration space.
L0s acceptable latency for the configuration
space.
L0s exit latency for active state power
management (separated reference clock) –
(latency between 64 ns – 128 ns).
L0s exit latency for active state power
management (common reference clock) –
(latency between 64 ns – 128 ns).
When set, enables the DLLP timer counter.
Reserved
Reserved
When set to 1b, the serial number capability is
enabled.
Extra NFTS (number of fast training signal),
which is added to the original requested
number of NFTS (as requested by the upstream
component).
Number of special sequence for L0s transition
to L0.
Description
Description
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