WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 269
WG82574IT S LBAC
Manufacturer Part Number
WG82574IT S LBAC
Description
CONTROLLER, ENET, INTEL 82574IT, 64PQFN
Manufacturer
Intel
Datasheet
1.WG82574IT_S_LBAC.pdf
(490 pages)
Specifications of WG82574IT S LBAC
Ethernet Type
IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
QFN
No. Of Pins
64
Package / Case
QFN
Interface Type
I2C, JTAG, PCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Programing Interface—82574 GbE Controller
Table 72.
9.1.5.1
9.1.5.2
9.1.5.3
Table 73.
The last Qword is not necessarily fully populated.
MSI-X Capability Structure
Capability ID, Offset 0xA0 (RO)
This field equals 0x11 indicating the linked list item as being the MSI-X registers.
Next Pointer, Offset 0xA1 (RO)
This field provides an offset to the next capability item in the capability list. Its value is
0x00 indicating that this is the last capability.
Message Control, Offset 0xA2 (R/W)
The register fields are listed in the following table.
MSI-X Message Control Field
1. Default value is read from the NVM
TS
RSV
FM
En
0xA0
0xA4
0xA8
Byte Offset
Field
10:0
13:11
14
15
Bits
0x001
0b
0b
0b
Default
Byte 3
Message Control (0x00090)
1
RO
RO
R/W
R/W
R/W
Byte 2
Table Size
System software reads this field to determine the MSI-X table
size N, which is encoded as N-1. For example, a returned value
of 0x00000001111 indicates a table size of 16.
Always return 0b on read. Write operation has no effect.
Function Mask
If set to 1b, all of the vectors associated with the function are
masked, regardless of their per-vector Mask bit states.
If set to 0b, each vector’s Mask bit determines whether the
vector is masked or not.
Setting or clearing the MSI-X Function Mask bit has no effect on
the state of the per-vector Mask bits.
MSI-X Enable
If set to 1b and the MSI Enable bit in the MSI Message Control
register is 0b, the function is permitted to use MSI-X to request
service and is prohibited from using its INTx# pin.
System configuration software sets this bit to enable MSI-X. A
software device driver is prohibited from writing this bit to mask
a function’s service request.
If 0b, the function is prohibited from using MSI-X to request
service.
Table Offset
PBA offset
Next Pointer (0x00)
Byte 1
Description
Capability ID (0x11)
Byte 0
Table BIR
PBA BIR
269
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