WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 9

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet—82574 GbE Controller
Revision History
February 2011
January 2011
January 2010
October 2009
August 2009
April 2009
February 2009
December 2008
October 2008
August 2008
June 2008
February 2008
February 2008
Date
Revision
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.7
1.6
Description
Initial public release.
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Revised section 14.6 “Product Package Thermal Specification” (added a Psi JT note after table 94).
Revised section 6.1.1.16 (PCIe Init Configuration 3 Word (Word 0x1A); bits 3:2).
Revised section 9.1.6.1.7 (Link CAP, Offset 0xEC, (RO); bits 11:10).
Updated section 6 to reflect latest NVM dev start image.
Updated section 8.8.1.3 (CBDM bit description).
Updated section 8.8.1.6 (MAC Filters description).
Updated section 8.8.2.2 (status data byte 1 bit 4 name changed to reserved).
Updated section 8.8.2.5 (MAC Filters description).
Updated section 13.5.5.3.
Removed section 13.5.5.7.1 (Signal Detect).
Changed support of up to 256 KB TCP segmentation (TSO v2) to 64 KB.
Removed note from section 14.6.
Added new section 13.10 (Assembly Process Flow).
Added supported Flash devices under Table 25.
Revised section 4.6.2 (MDIO and NVM Semaphore).
Revised table 51 (MAC Address Functionality).
Revised table 64 (bit 4 is now a reserved bit).
Revised section 10.2.2.5 (bits 7:5 descriptions).
Revised section 10.2.3.11 (bits 1:0 descriptions).
Revised section 13.5.5.3 (Layer 1 signal layer).
Revised section 13.8 (Device Disable).
Revised section 14 (removed heat sink information).
Revised section 3.3.2 (Supported NVM Devices).
Added new sections 12.6 (Flash AC specifications) and 12.7 (EEPROM AC specifications).
Updated section 7.1.11.3 (IPv6 table).
Updated section 12.7 “Oscillator/Crystal Specifications” (added Cload note).
Updated section 13.3.1.6 “Load Capacitance and Discrete Capacitors” (new crystal load capacitance formula).
Updated table 97 (Cload value).
Changed the pull-up value of AUX_PWR from 1 K to 10 K. in the schematic checklist.
Changed “calibration load” to “Cload” in the schematic checklist.
Updated Section 8 “System Manageability”.
Removed section 8.9.4.1.
Updated section 13.3.1.6.
Removed reference schematics.
Updated sections 4.5.2, 7.1, 10.2.2.15, 12.6, 13.5.1, and 13.5.5.4.
Updated sections 6.3.1.3, 10.2.3.11, and 10.2.8.8.
Updated table 66.
Added section 8.12.2.3 - Set Intel Management Control Formats.
Added section 8.12.3.4 - Get Intel Management Control Formats.
Added section 10.2.3.12 - 3GPIO Control Register 2 - GCR2.
Updated section 13.1.4 - PCIe Routing.
Updated section 13.10 - Added “The XOR tree is output on the LED1 pin”.
Updated table 97 - Schematic Checklist.
Changed PCIe Rev. 2.0 (2.5 GHz) x1 to PCIe Rev. 1.1 (2.5 GHz) x1 in Section 1.0.
Added multi-drop application connectivity requirements to Section 13.6.1.2.
Updated title page - changed packet buffer size from 32 KB to 40 KB.
Updated section 15 - corrected NC-SI schematic checklist information.
Updated reference schematics - corrected NC-SI schematic information.
Updated section 5.2.
Added a note to Table 31.
Updated section 13.5.5.13.
Added 82574IT ordering information.
Quick fix provided which added Measured Power Consumption (Section 5.2). This is a temporary patch. Note that the fix
does not appear in the TOC or list of tables yet. This will be corrected next week.
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