WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 183

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inline Functions—82574 GbE Controller
7.4.4
Interrupt Moderation
The 82574L implements interrupt moderation to reduce the number of interrupts
software processes. The moderation scheme is based on a timer called ITR Interrupt
Throttle register). In general terms, the ITR defines an interrupt rate by defining the
time interval between consecutive interrupts.
The number of ITR registers is:
Software uses ITR to limit the rate of delivery of interrupts to the host CPU. It provides
a guaranteed inter-interrupt delay between interrupts asserted by the network
controller, regardless of network traffic conditions.
The following algorithm converts the inter-interrupt interval value to the common
'interrupts/sec' performance metric:
For example, if the interval is programmed to 500d, the 82574 guarantees the CPU is
not interrupted by it for at least 128 s from the last interrupt.
Inversely, inter-interrupt interval value can be calculated as:
The optimal performance setting for this register is very system and configuration
specific.
ITR rules:
Each time an interrupt event happens, the corresponding bit in the ICR is activated.
However, an interrupt message is not sent out on the PCIe* interface until the EITR
counter assigned to the proper MSI-X vector that supports the ICR bit has counted
down to zero. The EITR counter is reloaded after it has reached zero with its initial
value and the process repeats again. The interrupt flow should follow the following
diagram:
• Non MSI-X mode - a single ITR is used (ITR).
• MSI-X - a separate EITR is provided per MSI-X vector (EITR[0] is allocated to MSI-
• The maximum observable interrupt rate from the adapter should not exceed 7813
• The Extended Interrupt Throttle register should default to 0x0 upon initialization
X[0] and its corresponding interrupts, EITR[1] is allocated to MSI-X[1] and its
corresponding interrupts etc.)
interrupts/sec.
and reset.
Interrupts/sec = (256 * 10
Inter-interrupt interval = (256 * 10
-9
sec x interval) -1
-9
sec x interrupts/sec) -1
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