WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 139

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inline Functions—82574 GbE Controller
Note:
7.1.5.3
7.1.5.4
Descriptor Write-Back Format:
Light-blue fields are mutually exclusive by RXCSUM.PCSD
MRQ - Same as extended Rx descriptor.
Packet Checksum, IP Identification, RSS Hash - Same as extended Rx descriptor.
Extended Status, Extended Errors, VLAN Tag - Same as extended Rx descriptor.
Length 0 (16-Bit, Offset 8.32), Length [3:1] (3- x 16-Bit, Offset 16.16)
Upon a packet reception, hardware stores the packet data in one or more of the
indicated buffers. Hardware writes in the Length field of each buffer the number of
bytes that were posted in the corresponding buffer. If no packet data is stored in a
given buffer, hardware writes 0b in the corresponding Length field. Length covers the
data written to receive buffer including CRC bytes (if any).
Software is responsible for checking the Length fields of all buffers for data that
hardware might have written to the corresponding buffers.
Header Status (16-Bit, Offset 16.0):
HDRSP (bit 15) - Headers were split
Reserved (bits 14:10) - Reserved
Header Length (bits 9:0) - Packet header length
HDRSP (bit 15): The HDRSP bit (when active) indicates that hardware split the
headers from the packet data for the packet contained in this descriptor. The following
table identifies the packets that are supported by header/data split functionality. In
addition, packets with a data portion smaller than 16 bytes are not guaranteed to be
split. If the device is not configured to provide any offload that requires packet parsing,
the HDRSP bit is set to 0b' even if packet split was enabled. Non-split packets are
stored linearly in the buffers of the receive descriptor.
0
8
1
6
2
4
HDRSP
15
63
Packet Checksum
VLAN Tag
Length 3
14
48
RSS Hash
Reserved
47
IP Identification
Length 0
Length 2
10
9
32
Reserved
31
Extended Error
Length 1
HLEN (Header Length)
20
19
16
MRQ
15
Extended Status
Header Status
139
0
0