WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 161

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inline Functions—82574 GbE Controller
7.2.8
Note:
Note:
7.2.8.1
7.2.9
Transmit Interrupts
Hardware supplies the transmit interrupts described below. These interrupts are
initiated via the following conditions:
The transmit delay interrupt is indicated with the same interrupt bit as the transmit
write-back interrupt, TXDW. The transmit delay interrupt is only delayed in time as
previously discussed.
In MSI-X mode, the IDE bit in the transmit descriptor should not be set.
Delayed Transmit Interrupts
This mechanism allows software the flexibility of delaying transmit interrupts in order
to allow more time for new descriptors to be written to the memory ring and potentially
prevent an interrupt when the device's head pointer catches the tail pointer.
This feature is desirable, because a software device driver usually has no knowledge of
when it is going to be asked to send another frame. For performance reasons, it is best
to generate only one transmit interrupt after a burst of packets have been sent.
Transmit Data Storage
Data is stored in buffers pointed to by the descriptors. Alignment of data is on an
arbitrary byte boundary with the maximum size per descriptor limited only to the
maximum allowed length size. A packet typically consists of two (or more) descriptors,
one (or more) for the header and one (or more) for the actual data. Some software
implementations copy the header(s) and packet data into one buffer and use only one
descriptor per transmitted packet.
• Transmit Descriptor Ring Empty (ICR.TXQE) - All descriptors have been processed.
• Any write backs are performed; either with the RS bit set or when accumulated
• Transmit Delayed Interrupt (ICR.TXDW) - in conjunction with Interrupt Delay
• Transmit Descriptor Ring Low Threshold Hit (ICR.TXD_LOW) - Set when the total
The head pointer is equal to the tail pointer.
descriptors are written back when TXDCTL.WTHRESH descriptors have been
completed and accumulated; Transmit Descriptor Write Back (ICR.TXDW).
Enable (IDE), the TXDW indication is delayed per the TIDV and/or TADV registers.
The interrupt is set when one of the transmit interrupt countdown timers expire. A
transmit delayed interrupt is scheduled for a transmit descriptor with its RS bit set
and the IDE bit set. When a transmit delayed interrupt occurs, the TXDW interrupt
bit is set (just as when a transmit descriptor write-back interrupt occurs). This
interrupt can be masked in the same manner as the TXDW interrupt. This interrupt
is used frequently by software that performs dynamic transmit chaining by adding
packets one at a time to the transmit chain.
number of transmit descriptors available hits the low threshold specified in the
TXDCTL.LWTHRESH field in the Transmit Descriptor Control register. For the
purposes of this interrupt, number of transmit descriptors available is the
difference between the transmit descriptor tail and transmit descriptor head values,
minus the number of transmit descriptors that have been pre-fetched. Up to eight
descriptors can be pre-fetched.
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