WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 479

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Board Layout and Schematic Checklists—82574 GbE Controller
Clock Source
(Oscillator
Option)
EEPROM or
Flash
Memory
10/100/
1000Base-T
Interface
Traces
Section
Ensure the oscillator has a it's own local
power supply decoupling capacitor.
If the oscillator is shared or is more than
two inches away from the 82574, a back-
termination resistor should be placed near
the oscillator for each 82574.
Keep clock lines away from other digital
traces (especially reset signals), I/O ports,
board edge, transformers and differential
pairs.
The NVM can be placed a few inches away
from the 82574 to provide better spacing
of critical components.
Design traces for 100  differential
impedance (± 20%).
Avoid highly resistive traces (for example,
avoid four mil traces longer than four
inches).
If a LAN switch is used or the trace length
from the 82574 is greater than four
inches. It might be necessary to boost the
voltage at the center tap with a separate
power supply to optimize MDI
performance.
Make traces symmetrical.
Do not make 90° bends.
Avoid through holes (vias).
Keep traces close together inside a
differential pair.
Keep trace-to-trace length difference
within each pair to less than 50 mils.
Pair-to-pair trace length does not have to
be matched as differences are not critical.
Keep differential pairs more than seven
times the dielectric thickness away from
each other and other traces, including
NVM traces and parallel digital traces.
Ensure that line side MDI traces and line
side termination are at least 80 mils from
all other traces.
Keep traces at least 0.1 inches away from
the board edge.
Do not have stubs along the traces.
Digital signals on adjacent layers must
cross at 90° angles. Splits in power and
ground planes must not cross.
Check Item
This enables tuning to ensure that reflections do not distort the
clock waveform.
This reduces EMI.
Primary requirement for 10/100/1000 Mb/s Ethernet. Paired
50  traces do not make 100  differential. An impedance
calculator can be used to verify this.
If trace length is a problem, use thicker board dielectrics to
allow wider traces. Thicker copper is even better than wider
traces.
Consider using a second 82574 instead of a LAN switch and
long MDI traces. It is difficult to achieve excellent performance
with long traces and analog LAN switches. Additional
optimization effort is required to tune the system, the center
tap voltage, and magnetics modules.
Pairs should be matched at pads, vias and turns. Asymmetry
contributes to impedance mismatch.
Bevel corners with turns based on 45° angles
If vias are used, the budget is two per trace.
Traces should be kept within 10 mils regardless of trace
geometry.
This minimizes signal skew and common mode noise.
Improves long cable performance.
The difference between the length of longest pair and the
length of the shortest pair should be kept below two inches.
This minimizes crosstalk and noise injection. Tighter spacing is
allowed for the first 200 mils of trace near of the components.
This is to ensure the system can survive a high voltage on the
MDI cable. (Hi-POT)
This reduces EMI.
Stubs cause discontinuities that impact return loss.
Differential pairs should be run on different layers as needed to
improve routing.
Remarks
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