WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 64
WG82574IT S LBAC
Manufacturer Part Number
WG82574IT S LBAC
Description
CONTROLLER, ENET, INTEL 82574IT, 64PQFN
Manufacturer
Intel
Datasheet
1.WG82574IT_S_LBAC.pdf
(490 pages)
Specifications of WG82574IT S LBAC
Ethernet Type
IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
QFN
No. Of Pins
64
Package / Case
QFN
Interface Type
I2C, JTAG, PCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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4.3
4.3.1
64
In situations where the device is reset using the software reset CTRL.RST, the TX data
lines will be forced to all zeros. This causes a substantial number of symbol errors to be
detected by the link partner.
Power Up
Power-Up Sequence
Figure 9
Figure 9
Figure 15
4. The Wake-Up Management (WUM) registers include the following:
5. The following register fields do not follow the previously mentioned general rules:
6. The NVM is loaded only when the LAN function exits D3hot state.
— Wake-up filter control.
— IP address Valid.
— IPv4 address table
— IPv6 address table
— Flexible filter length table
— Flexible filter mask table
— Packet Buffer Allocation (PBA) - reset on Internal Power On Reset only.
— Packet Buffer Size (PBS) - reset on Internal Power On Reset only.
— LED configuration registers.
— The Aux Power Detected bit in the PCIe Device Status register is reset on
— FLA - reset on Internal Power On Reset only.
Internal Power On Reset and PCIe Power Good only.
through
shows a high-level view of the power sequence, while
provides a more detailed description of each state.
Figure 15
shows the 82574’s power-up sequencing.
82574 GbE Controller—Initialization
Figure 10
through
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