WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 283

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
10.1.1.4
10.1.1.5
10.1.1.5.1
Memory-Mapped Access to Expansion ROM
The external Flash can also be accessed as a memory-mapped expansion ROM.
Accesses to offsets starting from the Expansion ROM BAR reference the Flash, provided
that access is enabled through the NVM Initialization Control Word, and the Expansion
ROM BAR contains a valid (non-zero) base memory address.
I/O-Mapped Access to Internal Registers, Memories, and Flash
To support pre-boot operation (prior to the allocation of physical memory base
addresses), all internal registers, memories, and Flash can be accessed using I/O
operations. I/O accesses are supported only if:
When an I/O BAR is mapped, the I/O address range allocated opens a 32-byte window
in the system I/O address map. Within this window, two I/O addressable registers are
implemented:
The IOADDR register is used to specify a reference to an internal register, memory, or
Flash, and then the IODATA register is used as a window to the register, memory or
Flash address specified by IOADDR:
IOADDR (I/O Offset 0x00)
The IOADDR register must always be written as a Dword access. Writes that are less
than 32 bits are ignored. Reads of any size return a Dword of data. However, the
chipset or CPU might only return a subset of that Dword.
For software programmers, the IN and OUT instructions must be used to cause I/O
cycles to be used on the PCIe bus. Because writes must be to a 32-bit quantity, the
source register of the OUT instruction must be EAX (the only 32-bit register supported
by the OUT command). For reads, the IN instruction can have any size target register,
but it is recommended that the 32-bit EAX register be used.
Because only a particular range is addressable, the upper bits of this register are hard
coded to zero. Bits 31 through 20 cannot be written to and always read back as 0b.
At hardware reset (Internal Power On Reset) or PCI Reset, this register value resets to
0x00000000. Once written, the value is retained until the next write or reset.
0x00
0x04
0x08 – 0x1F
• An I/O Base Address Register (BAR) is allocated and mapped (BAR2)
• The BAR contains a valid (non-zero) value
• I/O address decoding is enabled in the PCIe configuration
• IOADDR
• IODATA
Offset
IOADDR
IODATA
Reserved
Abbreviation
Internal register, internal memory, or Flash location
address.
0x00000-0x1FFFF – Internal registers and memories.
0x20000-0x7FFFF – Undefined.
0x80000-0xFFFFF – Flash.
Data field for reads or writes to the Internal Register,
Internal Memory, or Flash Location as identified by
the current value in IOADDR. All 32 bits of this
register are read/write-able.
Reserved
Name
R/W
R/W
RO
R/
W
4 bytes
4 bytes
4 bytes
Size
283