WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 110

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1.1.16
110
15
14
13
12
11:10
9
8
7
6
5
4
3:2
1
0
Bit
Master_Enable
Scram_dis
Ack_Nak_Sch
Cache_Lsize
PCIE_Cap
IO_Sup
Packet_Size
Reserved
Reserved
Reserved
Reserved
Act_Stat_PM_Sup
Slot_Clock_Cfg
Loop back polarity
inversion
Name
PCIe Init Configuration 3 Word (Word 0x1A)
0b
0b
0b
0b
01b
1b
1b
0b
0b
0b
0b
0x3
1b
0b
Hardware
Default
0b
0b
0b
0b
01b
1b
1b
0b
0b
1b
1b
0x3
1b
0b
Setting
Image
NVM
When set to 1b, this bit enables the PHY to be a master
(upstream component/cross link functionality).
Scrambling Disable
When set to 1b, this bit disables the PCIe LFSR scrambling.
ACK/NAK Scheme
0b = Scheduled for transmission following any TLP.
1b = Scheduled for transmission according to time outs
specified in the PCIe specification.
Cache Line Size
0b = 64 bytes.
1b = 128 bytes.
Note: The value loaded must be equal to the actual cache line
size used by the platform, as configured by system software.
PCIe Capability Version
I/O Support (Effect I/O BAR Request)
0b = I/O is not supported.
1b = I/O is supported.
Default Packet Size
0b = 128 bytes.
1b = 256 bytes.
Reserved
Reserved
Reserved
Reserved
Determines support for Active State Link Power Management
(ASLPM). Loaded into the PCIe Active State Link PM Support
register.
Note: Changing the default value of this field might affect
certain power savings features of the 82574. However, in some
applications, it might be necessary to change this value as
explained in the Intel® 82574 Family Gigabit Ethernet
Controller Specification Update. Please refer to Erratum #20 for
more details.
When set, the 82574 uses the PCIe reference clock supplied on
the connector (for add-in solutions).
Check Polarity Inversion in Loop-Back Master Entry
During normal operation polarity is adjusted during link up.
When this bit is set, the receiver re-checks the polarity of Rx-
data and then inverts it accordingly, when entering a near-end
loopback. When cleared, polarity is not re-checked after link up.
82574 GbE Controller—Non-Volatile Memory (NVM) Map
Description