WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 275

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programing Interface—82574 GbE Controller
9.1.6.1.8
9.1.6.1.9
Link Control, Offset 0xF0, (RO)
This register controls PCIe link specific parameters.
Link Status, Offset 0xF2, (RO)
This register provides information about PCIe link-specific parameters. This is a read-
only register.
1:0
2
3
4
5
6
7
15:8
3:0
9:4
10
11
12
15:13
Bits
Bits
RW
RO
RW
RO
RO
RW
RW
RO
RO
RO
RO
RO
HwInit
RO
R/W
R/R
0001b
000001b
0b
0b
1b
0000b
00b
0b
0b
0b
0b
0b
0b
0x0
Default
Default
Active State Link PM Control
This field controls the active state PM supported on the link. Defined
encodings are:
00b = PM disabled.
01b = L0s entry supported.
10b = Reserved.
11b = L0s and L1 supported.
Reserved.
Read Completion Boundary.
Link Disable
Not applicable for end-point devices, hardwired to 0b.
Retrain Clock
Not applicable for end-point devices, hardwired to 0b.
Common Clock Configuration
When set, indicates that the 82574 and the component at the other end of the
link are operating with a common reference clock. A value of 0b indicates that
they operate with an asynchronous clock. This parameter affects the L0s exit
latencies.
Extended Sync
This bit, when set, forces extended Tx of FTS ordered set in FTS and extra
TS1 at exit from L0s prior to enter L0.
Reserved.
Link Speed
Indicates the negotiated link speed. 0001b is the only defined speed, which is
2.5 Gb/s.
Negotiated Link Width
Indicates the negotiated width of the link.
Relevant encoding for the 82574 is:
000001b x1
Link Training Error
Indicates that a link training error has occurred.
Link Training
Indicates that link training is in progress.
Slot Clock Configuration
When set, indicates that the 82574 uses the physical reference clock that the
platform provides on the connector. This bit must be cleared if the 82574 uses
an independent clock. Slot Clock Configuration bit is loaded from the
Slot_Clock_Cfg NVM bit.
Reserved
Description
Description
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