WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 62

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.0
4.1
4.2
62
Initialization
Introduction
This chapter discusses initialization steps. This includes:
Reset Operation
The 82574L reset sources are as follows:
• General hardware power-up state
• Basic device configuration
• Initialization of transmit and receive operation
• Link configuration and software reset capability
• Statistics initialization
• Internal Power On Reset- The 82574L has an internal mechanism for sensing the
• PE_RST_N - Indicates that both the power and the PCIe clock sources are stable; a
• Device Disable/Dr Disable - The 82574L enters a device disable mode when the
• In-band PCIe reset - The 82574L generates an internal reset in response to a
• D3hotD0 transition - This is also known as ACPI reset. The 82574L generates an
• Software Reset - Software can reset the 82574 by writing the Device Reset bit of
power pins. Once power is up and stable, the 82574 implements an internal reset.
This reset acts as a master reset of the entire chip. It is level sensitive, and while it
is 0b holds all of the registers in reset. Internal Power On Reset is an indication that
device power supplies are all stable. Internal Power On Reset changes state during
system power up.
value of 0b indicates reset active. This pin asserts an internal reset also after a
D3cold exit. Most units are reset on the rising edge of PE_RST_N. The only
exception is the PCIe unit, which is kept in reset while PE_RST_N is active.
DEV_OFF_N pin is asserted without shutdown (see
enters Dr disable mode when certain conditions are met in the Dr state (see
Section
Physical Layer (PHY) message from PCIe or when the PCIe link goes down (entry to
polling or detect state). This reset is equivalent to PCI reset in previous (PCI) GbE
controllers.
internal reset on the transition from D3hot power state to D0 (caused after
configuration writes from D3 to D0 power state). Note that this reset is per function
and resets only the function that transitioned from D3hot to D0.
the Device Control (CTRL.RST) register. The 82574L re-reads the per-function NVM
fields after a software reset. Bits that are normally read from the NVM are reset to
their default hardware values. Note that this reset is per function and resets only
the function that received the software reset. PCI configuration space
(configuration and mapping) of the device is unaffected.
5.4.4.3).
Section
82574 GbE Controller—Initialization
5.4.4.4). The 82574L