WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 322
WG82574IT S LBAC
Manufacturer Part Number
WG82574IT S LBAC
Description
CONTROLLER, ENET, INTEL 82574IT, 64PQFN
Manufacturer
Intel
Datasheet
1.WG82574IT_S_LBAC.pdf
(490 pages)
Specifications of WG82574IT S LBAC
Ethernet Type
IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
QFN
No. Of Pins
64
Package / Case
QFN
Interface Type
I2C, JTAG, PCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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10.2.4.2
10.2.4.3
322
Interrupt Throttling Register - ITR (0x000C4; R/W)
Software can use this register to prevent the condition of repeated, closely spaced,
interrupts to the host CPU, asserted by the 82574, by guaranteeing a minimum delay
between successive interrupts.
To independently validate configuration settings, software can use the following
algorithm to convert the inter-interrupt interval value to the common interrupts/sec
performance metric:
interrupts/sec = (256 x 10
For example, if the interval is programmed to 500 (decimal), the 82574 guarantees the
CPU is not interrupted by it for 128 s from the last interrupt. The maximum observable
interrupt rate from the 82574 should never exceed 7813 interrupts/sec.
Inversely, inter-interrupt interval value can be calculated as:
inter-interrupt interval = (256 x 10
The optimal performance setting for this register is very system and configuration
specific. An initial suggested range is 651- 5580 decimal (or 0x28B - 0x15CC).
Extended Interrupt Throttle - EITR (0x000E8 + 4 *n[n = 0..4]; R/W)
Each EITR is responsible for an MSI-X interrupt cause. The allocation of EITR-to-
interrupt cause is through the IVAR registers.
Software can use this register to prevent the condition of repeated, closely spaced,
interrupts to the host CPU, asserted by the network controller, by guaranteeing a
minimum delay between successive interrupts.
INTERVAL
Reserved
INTERVAL
Reserved
Field
Field
15:0
31:16
15:0
31:16
Bit(s)
Bit(s)
0x0
0x0
0x0
0x0
Initial
Initial
Value
Value
-9
sec x interval)-1
Minimum Inter-Interrupt Intervall
The interval is specified in 256 ns increments. Zero disables interrupt
throttling logic.
Reserved
Should be written with 0x0 to ensure future compatibility.
Minimum Inter-Interrupt Interval
The interval is specified in 256 ns increments. Zero disables interrupt
throttling logic.
Reserved
Should be written with 0x0 to ensure future compatibility.
-9
sec x interrupts/sec) -1
82574 GbE Controller—Driver Programing Interface
Description
Description
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