WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 158

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2.4.1
Note:
7.2.4.2
158
Descriptors between the head and the tail pointers are descriptors that have been
prepared by software and are owned by hardware.
Transmit Descriptor Fetching
The descriptor processing strategy for transmit descriptors is essentially the same as
for receive descriptors.
When the on-chip descriptor queue is empty, a fetch occurs as soon as any descriptors
are made available (host writes to the tail pointer). Hardware might elect to perform a
fetch which is not a multiple of cache line size. The hardware performs this non-aligned
fetch if doing so results in the next descriptor fetch being aligned on a cache line
boundary. This enables the descriptor fetch mechanism to be most efficient in the cases
where it has fallen behind software.
After the initial fetch of descriptors, as the on-chip buffer empties, the hardware can
decide to pre-fetch more transmit descriptors if the number of on-chip descriptors drop
below TXDCTL.PTHRESH and enough valid descriptors TXDCT is performed.
The 82574L NEVER fetches descriptors beyond the descriptor tail pointer.
Transmit Descriptor Write Back
The descriptor write-back policy for transmit descriptors is similar to that for receive
descriptors with a few additional factors.
There are three factors: the Report Status (RS) bit in the transmit descriptor, the write
back threshold (TXDCTL.WTHRESH) and the Interrupt Delay Enable (IDE) bit in the
transmit descriptor.
Descriptors are written back in one of three cases:
• TXDCTL.WTHRESH = zero, IDE = zero and a descriptor with RS set to 1b is ready
• IDE = 1b and the Transmit Interrupt Delay (TIDV) register timer expires, this timer
• TXDCTL.WTHRESH > zero and the write back of the full descriptors are performed
to be written back, for this condition write backs are immediate. The device writes
back only the status byte of the descriptor (TDESCR.STA) and all other bytes of the
descriptor are left unchanged.
is used to force a timely write back of descriptors. Timer expiration flushes any
accumulated descriptors and sets an interrupt event.
only when TXDCTL.WTHRESH number of descriptors are ready for a write back.
82574 GbE Controller—Inline Functions