UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 217
![8BIT MCU, 128K FLASH, 7K RAM, LQFP](/photos/19/1/190186/ge64lqfp05-40_sml.jpg)
UPD78F0890GK(A)-GAJ-AX
Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0890GKA-GAJ-AX.pdf
(732 pages)
Specifications of UPD78F0890GK(A)-GAJ-AX
Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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(2) Setting LVS0n and LVR0n
Set LVS0n and LVR0n using the following procedure.
Caution Be sure to set LVS0n and LVR0n following steps <1>, <2>, and <3> above.
<1> The TO0n pin output goes high when LVS0n and LVR0n = 10.
<2> The TO0n pin output goes low when LVS0n and LVR0n = 01 (the pin output remains unchanged from the
<3> The timer starts operating when TMC0n3 and TMC0n2 are set to 01, 10, or 11. Because LVS0n and
<4> The output level of the TO0n pin is inverted each time an interrupt signal (INTTM00n) is generated.
Remark n = 0 to 3
high level even if LVS0n and LVR0n are cleared to 00).
LVR0n were set to 10 before the operation was started, the TO0n pin output starts from the high level.
After the timer starts operating, setting LVS0n and LVR0n is prohibited until TMC0n3 and TMC0n2 = 00
(disabling the timer operation).
Step <2> can be performed after <1> and before <3>.
Setting
Setting
Figure 7-53. Example of Flow for Setting LVS0n and LVR0n Bits
Setting
TOC0n.OSPE0n, TOC0n4, TOC0n1
(TMC0n3, TMC0n2)
Setting
TOC0n.LVS0n bit
TOC0n.LVR0n bit
TMC0n.TMC0n3, TMC0n2
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03
INTTM00n signal
TO0n pin output
TOC0n.LVS0n, LVR0n
Figure 7-54. Timing Example of LVR0n and LVS0n
Operable bits
TOC0n.TOE0n
User’s Manual U17554EJ4V0UD
bit
00
bits
bits
<1>
bits
<2> <1> <3> <4>
<1> Setting of timer output operation
<2> Setting of timer output F/F
<3> Enabling timer operation
01, 10, or 11
<4>
<4>
217
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