UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 639
![8BIT MCU, 128K FLASH, 7K RAM, LQFP](/photos/19/1/190186/ge64lqfp05-40_sml.jpg)
UPD78F0890GK(A)-GAJ-AX
Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0890GKA-GAJ-AX.pdf
(732 pages)
Specifications of UPD78F0890GK(A)-GAJ-AX
Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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8-bit
operation
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Instruction
Group
2.
3.
2. This clock cycle applies to the internal ROM program.
SUB
SUBC
AND
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Except “r = A”
Mnemonic
register (PCC).
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
CHAPTER 26 INSTRUCTION SET
Note 3
Note 3
Note 3
User’s Manual U17554EJ4V0UD
Bytes
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
Note 1
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
Clocks
Note 2
8
8
8
−
−
−
5
9
5
9
9
9
−
−
−
5
9
5
9
9
9
−
−
−
5
9
5
9
9
9
A, CY ← A − byte
(saddr), CY ← (saddr) − byte
A, CY ← A − r
r, CY ← r − A
A, CY ← A − (saddr)
A, CY ← A − (addr16)
A, CY ← A − (HL)
A, CY ← A − (HL + byte)
A, CY ← A − (HL + B)
A, CY ← A − (HL + C)
A, CY ← A − byte − CY
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
r, CY ← r − A − CY
A, CY ← A − (saddr) − CY
A, CY ← A − (addr16) − CY
A, CY ← A − (HL) − CY
A, CY ← A − (HL + byte) − CY
A, CY ← A − (HL + B) − CY
A, CY ← A − (HL + C) − CY
A ← A ∧ byte
(saddr) ← (saddr) ∧ byte
A ← A ∧ r
r ← r ∧ A
A ← A ∧ (saddr)
A ← A ∧ (addr16)
A ← A ∧ [HL]
A ← A ∧ [HL + byte]
A ← A ∧ [HL + B]
A ← A ∧ [HL + C]
CPU
) selected by the processor clock control
Operation
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
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×
Flag
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
639
×
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