UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 341
![8BIT MCU, 128K FLASH, 7K RAM, LQFP](/photos/19/1/190186/ge64lqfp05-40_sml.jpg)
UPD78F0890GK(A)-GAJ-AX
Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0890GKA-GAJ-AX.pdf
(732 pages)
Specifications of UPD78F0890GK(A)-GAJ-AX
Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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1. Stop bit length: 1
2. Stop bit length: 2
Remark n = 0, 1
(c) Normal transmission
When bit 7 (POWER6n) of asynchronous serial interface operation mode register 6n (ASIM6n) is set to 1 and
bit 6 (TXE6n) of ASIM6n is then set to 1, transmission is enabled. Transmission can be started by writing
transmit data to transmit buffer register 6n (TXB6n). The start bit, parity bit, and stop bit are automatically
appended to the data.
When transmission is started, the data in TXB6n is transferred to transmit shift register 6n (TXS6n). After
that, the data is sequentially output from TXS6n to the T
parity and stop bits set by ASIM6n are appended and a transmission completion interrupt request (INTST6n)
is generated.
Transmission is stopped until the data to be transmitted next is written to TXB6n.
Figure 14-23 shows the timing of the transmission completion interrupt request (INTST6n). This interrupt
occurs as soon as the last stop bit has been output.
T
T
X
X
D6n (output)
D6n (output)
INTST6n
INTST6n
Figure 14-23. Normal Transmission Completion Interrupt Request Timing
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61
Start
Start
D0
D0
User’s Manual U17554EJ4V0UD
D1
D1
D2
D2
X
D6n pins. When transmission is completed, the
D6
D6
D7
D7
Parity
Parity
Stop
Stop
341
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