UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 644

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

644
Conditional
branch
CPU
control
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Instruction
Group
2.
2. This clock cycle applies to the internal ROM program.
BT
BF
BTCLR
DBNZ
SEL
NOP
EI
DI
HALT
STOP
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Mnemonic
register (PCC).
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
B, $addr16
C, $addr16
Saddr, $addr16
RBn
Operands
CHAPTER 26 INSTRUCTION SET
User’s Manual U17554EJ4V0UD
Bytes
3
4
3
3
3
4
4
3
4
3
4
4
3
4
3
2
2
3
2
1
2
2
2
2
Note 1
10
10
10
10
10
8
−
8
−
−
8
−
−
8
−
6
6
8
4
2
−
−
6
6
Clocks
Note 2
11
11
11
11
11
11
12
12
12
12
10
9
−
9
−
−
−
−
−
−
6
6
−
−
PC ← PC + 3 + jdisp8 if(saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 3 + jdisp8 if PSW.bit = 1
PC ← PC + 3 + jdisp8 if (HL).bit = 1
PC ← PC + 4 + jdisp8 if(saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW. bit = 0
PC ← PC + 3 + jdisp8 if (HL).bit = 0
PC ← PC + 4 + jdisp8
if(saddr.bit) = 1
then reset(saddr.bit)
PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PC ← PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
B ← B − 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C −1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
(saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if(saddr) ≠ 0
RBS1, 0 ← n
No Operation
IE ← 1(Enable Interrupt)
IE ← 0(Disable Interrupt)
Set HALT Mode
Set STOP Mode
CPU
) selected by the processor clock control
Operation
Z AC CY
×
Flag
×
×