UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 560

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the
560
Multiplier/divider
Reset function
Low-voltage detector
Interrupt
2
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
These values vary depending on the reset source.
Register
RESF
LVIM
LVIS
Table 19-2. Hardware Statuses After Reset Acknowledgment (3/3)
Reset Source
WDTRF bit
LVIRF bit
Remainder data register 0 (SDR0)
Multiplication/division data register A0 (MDA0H, MDA0L)
Multiplication/division data register B0 (MDB0)
Multiplier/divider control register 0 (DMUC0)
Reset control flag register (RESF)
Low-voltage detection register (LVIM)
Low-voltage detection level selection register (LVIS)
Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H)
Mask flag registers 0L, 0H, 1L, 1H (MK0L, MK0H, MK1L, MK1H)
Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L,
PR1H)
External interrupt rising edge enable register (EGP)
External interrupt falling edge enable register (EGN)
Cleared (0)
Cleared (00H)
RESET Input
CHAPTER 19 RESET FUNCTION
Hardware
User’s Manual U17554EJ4V0UD
Cleared (0)
Cleared (00H)
Reset by POC
Set (1)
Held
Cleared (00H)
Reset by WDT
Held
Set (1)
Held
Reset by LVI
0000H
0000H
0000H
00H
00H
00H
00H
FFH
FFH
00H
00H
00H
Acknowledgment
Status After Reset
Note2
Note2
Note2
Note 1

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