UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 553

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

at 0000H and 0001H when the reset signal is generated.
circuit voltage detection, and each item of hardware is set to the status shown in Tables 19-1 and 19-2. Each pin is
high impedance during reset signal generation or during the oscillation stabilization time just after a reset release,
except for P130, which is low-level output.
level is input to the RESET pin and program execution is started with the internal high-speed oscillation clock after
reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the
internal high-speed oscillation clock (see Figures 19-2 to 19-4) after reset processing. Reset by POC and LVI circuit
power supply detection is automatically released when V
execution starts using the internal high-speed oscillation clock (see CHAPTER 21 POWER-ON-CLEAR CIRCUIT
and CHAPTER 22 LOW-VOLTAGE DETECTOR) after reset processing.
The following four operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets have no functional differences. In both cases, program execution starts at the address
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high
Cautions 1. For an external reset, input a low level for 10
2. During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and
3. When the STOP mode is released by a reset, the STOP mode contents are held during reset
internal low-speed oscillation clock stop oscillating. External main system clock input and
external subsystem clock input become invalid.
input. However, the port pins become high-impedance, except for P130, which is set to
low-level output.
CHAPTER 19 RESET FUNCTION
User’s Manual U17554EJ4V0UD
DD
≥ V
POC
μ
s or more to the RESET pin.
or V
DD
≥ V
LVI
after the reset, and program
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