UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 400

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

400
Reference: The CAN standard ISO 11898 specification defines the segments constituting the data bit time as
Remark IPT : Information Processing Time
Sync Segment
(Synchronization Segment)
Prop Segment
Phase Segment 1
Phase Segment 2
SJW
Segment Name
Figure 16-19. Reference: Configuration of Data Bit Time Defined by CAN Specification
TQ : Time Quanta
shown in Figure 16-19.
Sync segment
1
Programmable to 1 to 8
or more
Programmable to 1 to 8
Phase Segment 1 or
IPT, whichever greater
Programmable from
1TQ to length of
segment 1 or 4TQ,
whichever is smaller
Segment Length
Prop segment
CHAPTER 16 CAN CONTROLLER
User’s Manual U17554EJ4V0UD
Data bit time(DBT)
Phase segment 1
This segment starts at the edge where the level changes
from recessive to dominant when hard-synchronization is
established.
This segment absorbs the delay of the output buffer, CAN
bus, and input buffer.
The length of this segment is set so that ACK is returned
before the start of phase segment 1.
Time of prop segment ≥ (Delay of output buffer) + 2 x
(Delay of CAN bus) + (Delay of input buffer)
This segment compensates for an error of data bit time.
The longer this segment, the wider the permissible range
but the slower the communication speed.
This width sets the upper limit of expansion or contraction
of the phase segment during resynchronization.
Sample point (SPT)
Phase segment 2
Description
SJW