UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 393
![8BIT MCU, 128K FLASH, 7K RAM, LQFP](/photos/19/1/190186/ge64lqfp05-40_sml.jpg)
UPD78F0890GK(A)-GAJ-AX
Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0890GKA-GAJ-AX.pdf
(732 pages)
Specifications of UPD78F0890GK(A)-GAJ-AX
Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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mode by bus operation (the CAN stop mode is controlled by CPU access).
16.3.6 Error control function
Bit error
Stuff error
CRC error
Form error
ACK error
The controller is woken up from the CAN sleep mode by bus operation but it is not woken up from the CAN stop
(1) Error types
(2) Output timing of error frame
(3) Processing in case of error
Type
The transmission node re-transmits the data frame or remote frame after the error frame (However, it does
not re-transmit the frame in the single-shot mode.).
Bit error, stuff error,
form error, ACK error
CRC error
Comparison of output level and
level on the bus
Check the receive data at the
stuff bit
Comparison of the CRC
sequence generated from the
receive data and the received
CRC sequence
Field/frame check of the fixed
format
Check of the ACK slot by the
transmitting node
Type
Detection Method
Description of Error
Error frame output is started at the timing of the bit following the detected error.
Error frame output is started at the timing of the bit following the ACK delimiter.
Table 16-12. Output Timing of Error Frame
CHAPTER 16 CAN CONTROLLER
Table 16-11. Error Types
User’s Manual U17554EJ4V0UD
Mismatch of levels
6 consecutive bits
of the same output
level
Mismatch of CRC
Detection of fixed
format violation
Detection of
recessive level in
ACK slot
Detection
Condition
Output Timing
Transmitting/
receiving node
Receiving node
Receiving node
Receiving node
Transmitting node
Transmission/
Reception
Detection State
Bit that outputting data on the
bus at the start of frame to end of
frame, error frame and overload
frame.
Start of frame to CRC sequence
CRC field
CRC delimiter
ACK field
End of frame
Error frame
Overload frame
ACK slot
Field/Frame
393
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