UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 401

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(3) Synchronizing data bit
- The receiving node establishes synchronization by a level change on the bus because it does not have a
- The transmitting node transmits data in synchronization with the bit timing of the transmitting node.
(a) Hard-synchronization
sync signal.
This synchronization is established when the receiving node detects the start of frame in the interframe
space.
- When a falling edge is detected on the bus, that TQ means the sync segment and the next segment is
Figure 16-20. Hard-synchronization at Recognition of Dominant Level during Bus Idle
Bit timing
CANbus
the prop segment. In this case, synchronization is established regardless of SJW.
Interframe space
Sync
segment
CHAPTER 16 CAN CONTROLLER
User’s Manual U17554EJ4V0UD
Prop
segment
Start of frame
Phase
segment 1
Phase
segment 2
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