UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 374
![8BIT MCU, 128K FLASH, 7K RAM, LQFP](/photos/19/1/190186/ge64lqfp05-40_sml.jpg)
UPD78F0890GK(A)-GAJ-AX
Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0890GKA-GAJ-AX.pdf
(732 pages)
Specifications of UPD78F0890GK(A)-GAJ-AX
Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11
Figure 15-12. Output Operation of First Bit (2/2)
(c) Type 2: CKP1n = 0, DAP1n = 1
SCK1n
Writing to SOTB1n or
reading from SIO1n
SOTB1n
SIO1n
Output latch
SO1n
First bit
2nd bit
3rd bit
(d) Type 4: CKP1n = 1, DAP1n = 1
SCK1n
Writing to SOTB1n or
reading from SIO1n
SOTB1n
SIO1n
Output latch
SO1n
First bit
2nd bit
3rd bit
The first bit is directly latched by the SOTB1n register at the falling edge of the write signal of the SOTB1n
register or the read signal of the SIO1n register, and output from the SO1n pin via an output selector. Then, the
value of the SOTB1n register is transferred to the SIO1n register at the next falling (or rising) edge of SCK1n, and
shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin.
The second and subsequent bits are latched by the SIO1n register to the output latch at the next rising (or falling)
edge of SCK1n, and the data is output from the SO1n pin.
Remark n = 0, 1
374
User’s Manual U17554EJ4V0UD
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