W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet
W83877ATG
Specifications of W83877ATG
Related parts for W83877ATG
W83877ATG Summary of contents
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... W83877ATF W83877ATG WINBOND I/O ...
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... DATES 1 n.a. 07/29/97 1,3,6,49,50,98,14 2 04/10/98 0,141,142,170 n.a. 03/21/05 3 N.A. 11/16/ W83877ATF/W83877ATG VERSION VERSION ON WEB 0.50 First published. 0.51 A1 Typo correction and data calibrated 0.6 Add lead-free package version 1.0 N.A. Update to version 1.0 Publication Release Date:November 2006 - I - MAIN CONTENTS Version 1.0 ...
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... Universal Asynchronous Receiver/Transmitter (UART A, UART B) ...................................... 37 6.2 Register Address .................................................................................................................... 38 6.2.1 UART Control Register (UCR) (Read/Write) ............................................................................39 6.2.2 UART Status Register (USR) (Read/Write) ..............................................................................40 6.2.3 Handshake Control Register (HCR) (Read/Write) ....................................................................41 6.2.4 Handshake Status Register (HSR) (Read/Write)......................................................................42 6.2.5 UART FIFO Control Register (UFR) (Write only)......................................................................43 W83877ATF/W83877ATG - II - ...
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... Register A) Mode = 111 ..........................................................................90 7.3.9 cnfgB (Configuration Register B) Mode = 111 ..........................................................................90 7.3.10 ecr (Extended Control Register) Mode = all..............................................................................91 7.3.11 Bit Map of ECP Port Registers .................................................................................................92 7.3.12 ECP Pin Descriptions ...............................................................................................................93 7.3.13 ECP Operation .........................................................................................................................94 7.3.14 FIFO Operation ........................................................................................................................94 W83877ATF/W83877ATG Publication Release Date:November 2006 - III - Version 1.0 ...
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... Configuration Register 12 (CR12), default = 00H ...................................................................118 11.2.19 Configuration Register 13 (CR13), default = 00H ...................................................................118 11.2.20 Configuration Register 14 (CR14), default = 00H ...................................................................119 11.2.21 Configuration Register 15 (CR15), default = 00H ...................................................................120 11.2.22 Configuration Register 16 (CR16), default = 04H ...................................................................122 11.2.23 Configuration Register 17 (CR17), default = 00H ...................................................................123 W83877ATF/W83877ATG - IV - ...
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... Power Management Timer .....................................................................................................152 11.4 ACPI Registers (ACPIRs) ..................................................................................................... 153 11.4.1 Power Management 1 Status Register 1 (PM1STS1) ............................................................153 11.4.2 Power Management 1 Status Register 2 (PM1STS2) ............................................................154 11.4.3 Power Management 1 Enable Register 1(PM1EN1)...............................................................155 11.4.4 Power Management 1 Enable Register 2 (PM1EN2)..............................................................155 W83877ATF/W83877ATG Publication Release Date:November 2006 - V - Version 1.0 ...
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... FDC....................................................................................................................................... 174 13.2 UART/Parallel ....................................................................................................................... 175 13.3 Parallel Port......................................................................................................................... 177 14. APPLICATION CIRCUITS ............................................................................................................. 183 14.1 Parallel Port Extension FDD ................................................................................................. 183 14.2 Parallel Port Extension 2FDD ............................................................................................... 184 14.3 Four FDD Mode .................................................................................................................... 184 15. ORDERING INFORMATION ......................................................................................................... 185 16. HOW TO READ THE TOP MARKING........................................................................................... 185 17. PACKAGE DIMENSIONS.............................................................................................................. 186 W83877ATF/W83877ATG - VI - ...
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... Furthermore, the configurable PnP features are compatible with the plug-and-play feature TM demand of Windows 95 , which makes system resource allocation more efficient than ever. Another benifit is that W83877ATF/ATG has the same pin assignment as W83877F, W83877AF, W83877TF. This makes the design very flexible. W83877ATF/W83877ATG TM PC97 Hardware Design Guide. IRQs, Publication Release Date:November 2006 - ...
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... Support 3-mode FDD, and its Windows95TM driver • 16-byte data FIFOs UART: • Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs • MIDI compatible • Fully programmable serial-interface characteristics: − 8-bit characters − Even, odd or no parity bit generation/detection − stop bits generation W83877ATF/W83877ATG - 2 - ...
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... Full 16-bit address decode (UART B pin option) • PNF pin (Printer-Not-Floppy pin) for distinguishing printer port connection --- FDD or Printer; unique for notebook application of external floppy through printer port Package: • 100-pin QFP (W83877ATF/ATG) W83877ATF/W83877ATG TM TM Windows 95 and Windows 98 Publication Release Date:November 2006 - 3 - ...
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... PIN CONFIGURATION / INDEX STEP X 83 DSA X 84 DSB RWC X 88 HEAD X 89 DIR X GND 90 X IRQ_H IRQ_B X 93 IRQIN X 94 IRRX2 X 95 IRTX2 X 96 IRQ_A DACK_B X 99 IRQ_F X 100 DRQ_B W83877ATF/W83877ATG / RIB 50 X DCDB DSRB X CTSB DTRB X 45 RTSB X 44 IRQ_C ...
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... OUT 98 IN DACK_B ts W83877ATF/W83877ATG System data bus bits 0-7. System address bus bits 0-10. In EPP Mode, this pin is the I/O Channel Ready output to extend the host read/write cycle. Master Reset. Active high low during normal operations. Active low chip select signal. ...
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... IRQ_F 99 OUT IRQ_G 1 OUT DRQ_D OUT IRSL2 OUT PCICLK IN W83877ATF/W83877ATG DMA request signal C. 12t DMA acknowledge signal C. ts Interrupt request input. ts DMA request signal D. 12t IR module mode selection 2. 12t When input, acts as a function of high speed IR receiving terminal. When output selected, acts module mode 12ts selection 0 ...
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... IN t INt RIB 50 A15 INt W83877ATF/W83877ATG FUNCTION Interrupt request signal H. IR module mode selection 2. DMA acknowledge signal D. Serial Interrupt output, when the function of the serial IRQ is set to logic 1 defined in the CR31.bit2 (IRQMODS). 24MHz/48MHZ clock input. CLKINSEL bit in CR2C register should be correctly reset/set according to the input frequency. ...
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... OUT IRRX2 W83877ATF/W83877ATG Serial Input of COM A. Used to receive serial data from the communication link. Serial Input of COM B. Used to receive serial data from the communication link. When infrared function is selected, acts as infrared input. UART A Serial Output. Used to transmit serial data out to the communication link ...
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... OD 12 INt PE 27 OD12 OD12 W83877ATF/W83877ATG FUNCTION PRINTER MODE: BUSY An active high input indicates that the printer is not ready to receive data. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. ...
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... INIT W83877ATF/W83877ATG FUNCTION PRINTER MODE: SLCT An active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WE2 This pin is for Extension FDD B ...
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... PD1 W83877ATF/W83877ATG FUNCTION PRINTER MODE: AFD An active low output from this pin causes the printer to auto feed a line after a line is printed. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. ...
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... PD5 14 I/O 24t - - W83877ATF/W83877ATG FUNCTION PRINTER MODE: PD2 Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WP2 This pin is for Extension FDD B; the function of this pin is the same as that of the WP pin ...
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... TRAK0 cs W83877ATF/W83877ATG FUNCTION PRINTER MODE: PD6 Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE:This pin is a tri-state output. EXTENSION. 2FDD MODE: MOA2 This pin is for Extension FDD A; its function is the same as that of the MOA pin ...
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... GND 65, 90 W83877ATF/W83877ATG FUNCTION This schmitt input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by an approximately 1K ohm resistor. The resistor can be disabled by bit 4 of CR6 (FIPURDWN) ...
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... Byte 15 Byte FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte W83877ATF/W83877ATG MAXIMUM DELAY TO SERVICING AT 500K BPS Data Rate 1 × 16 μ 1.5 μ 14.5 μ × 16 μ 1.5 μ 30.5 μ × 16 μ 1.5 μ 6.5 μ × 16 μ 1.5 μ 238.5 μ S MAXIMUM DELAY TO SERVICING AT 1M BPS Data Rate 1 × ...
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... A single command puts the FDC into perpendicular mode. All other commands operate as they do normally. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. W83877ATF/W83877ATG - 16 - ...
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... HDS: Head number select HLT: Head Load Time HUT: Head Unload Time LOCK: Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset MFM: MFM or FM Mode MT: Multitrack N: The number of data bytes written in a sector W83877ATF/W83877ATG Publication Release Date:November 2006 - 17 - Version 1.0 ...
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... C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution -------------------- ST0 ----------------------- R R Result -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83877ATF/W83877ATG HDS - REMARKS Command codes 1 0 DS1 DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after ...
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... C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution R -------------------- ST0 ----------------------- Result R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83877ATF/W83877ATG HDS - REMARKS Command codes 0 0 DS1 DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution ...
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... Result R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ (4) Read ID PHASE R Command W 0 MFM W 0 Execution R -------------------- ST0 ----------------------- Result R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- ---------------------- C ------------------------ R R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83877ATF/W83877ATG HDS DS1 HDS DS1 - REMARKS Command codes 1 0 DS0 Sector ID information prior to command execution Data transfer between the FDD and system ...
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... ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- -------------------- DTL/SC ------------------- Execution R -------------------- ST0 ----------------------- Result R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ (6) Version PHASE R Command W 0 Result W 1 W83877ATF/W83877ATG HDS REMARKS Command codes 1 0 DS1 DS0 Sector ID information prior to command execution No data transfer takes place Status information after ...
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... PHASE R Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution R -------------------- ST0 ----------------------- Result R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83877ATF/W83877ATG HDS HDS DS1 - REMARKS 0 1 Command codes DS1 DS0 Sector ID information prior to Command execution Data transfer between the FDD and system ...
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... Execution W ---------------------- H ------------------------ for Each Sector W ---------------------- R ------------------------ Repeat: W ---------------------- N ------------------------ R -------------------- ST0 ----------------------- Result R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- (10) Recalibrate PHASE R Command Execution (11) Sense Interrupt Status PHASE R Command Result R ---------------- ST0 ------------------------- R ---------------- PCN ------------------------- W83877ATF/W83877ATG HDS REMARKS Command codes 0 1 DS1 DS0 Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte ...
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... Specify PHASE R Command ---------SRT ----------- | --------- HUT ---------- | W |------------ HLT -----------------------------------| ND (13) Seek PHASE R Command -------------------- NCN ----------------------- Execution R (14) Configure PHASE R Command EIS --------------------PRETRK ---------------------- | Execution (15) Relative Seek PHASE R Command W 1 DIR -------------------- RCN ---------------------------- | W83877ATF/W83877ATG HDS DS1 ------ FIFOTHR ---- EFIFO POLL | HDS DS1 - REMARKS 1 Command codes D0 REMARKS Command codes ...
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... SRT ----------- | -------- HUT ---------- R ------------ HLT -------------------------------------| ND -------------------- SC/EOT -------------------- R LOCK R 0 EIS EFIFO POLL| R --------------------PRETRK --------------------- R (17) Perpendicular Mode PHASE R Command (18) Lock PHASE R/W D7 Command W LOCK Result R 0 (19) Sense Drive Status PHASE R Command Result R ---------------- ST3 ------------------------- (20) Invalid PHASE R Command W ------------- Invalid Codes ----------------- Result R -------------------- ST0 ---------------------- W83877ATF/W83877ATG GAP --- FIFOTHR ---- LOCK ...
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... A second drive has been installed 1 A second drive has not been installed STEP (Bit 5): This bit indicates the complement of STEP output. TRAK0 (Bit 4): This bit indicates the value of TRAK0 input. W83877ATF/W83877ATG REGISTER READ SA REGISTER SB REGISTER TD REGISTER MS REGISTER DT (FIFO) REGISTER DI REGISTER ...
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... This bit indicates the value of the floppy disk interrupt output. DRQ (Bit 6): This bit indicates the value of DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of latched STEP output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0 input. W83877ATF/W83877ATG ...
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... This bit indicates the status of DO REGISTER bit 0 (drive select bit 0). WDATA Toggle (Bit 4): This bit changes state at every rising edge of the WD output pin. RDATA Toggle (Bit 3): This bit changes state at every rising edge of the RDATA output pin. WE (Bit 2): This bit indicates the complement of the WE output pin. MOT EN B (Bit 1) W83877ATF/W83877ATG ...
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... WE F/F (Bit 2): This bit indicates the complement of latched WE output pin. DSD (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected DSC (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected W83877ATF/W83877ATG Publication Release Date:November 2006 - 29 - DSC DSD ...
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... This register also holds the media ID, drive type, and floppy boot drive information of the floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are as follows: If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows: 7 W83877ATF/W83877ATG 3 1-0 2 Drive Select: 00 select drive A ...
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... The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by the DR REGISTER. The real data rate is determined by the most recent write to either of the DR REGISTER or CC REGISTER. W83877ATF/W83877ATG TAPE SEL ...
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... DATA RATE 250 KB/S 300 KB/S 500 KB/S 1 MB/S 2 MB/S W83877ATF/W83877ATG PRECOMPENSATION DELAY 250K - 1Mbps Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 0.00 nS (disabled) DEFAULT PRECOMPENSATION DELAYS - 32 - DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET 2 Mbps Tape drive Default Delays 20 ...
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... In the W83877ATF/ATG, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. Status Register 0 (ST0) 7 1-0 4 W83877ATF/W83877ATG US1, US0 Drive Select: 00 Drive A selected 01 Drive B selected 10 Drive C selected 11 Drive D selected HD Head address: 1 Head selected 0 Head selected ...
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... Status Register 3 (ST3) 7 W83877ATF/W83877ATG 0 Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted. NW (Not Writable write Protect signal is detected from the diskette drive during execution of write data. ND (No DATA specified sector cannot be found during execution of a read, write or verifly data. ...
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... These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings corresponding to the individual data rates. HIGH DENS (Bit 0): 0 500 KB MB/S data rate (high density FDD) 1 250 KB/S or 300 KB/S data rate In the PS/2 Model 30 mode, the bit definitions are as follows: W83877ATF/W83877ATG ...
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... In the PS/2 Model 30 mode, the bit definitions are as follows Bit 7-3: Reserved. These bits should be set to 0. NOPREC (Bit 2): This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. W83877ATF/W83877ATG ...
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... The UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16- byte FIFOs for both receive and transmit mode. W83877ATF/W83877ATG Publication Release Date:November 2006 - 37 - Version 1.0 ...
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... BDLAB = 1 Latch Low Baudrate 9 Divisor BHL Bit 8 BDLAB = 1 Latch High *: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 mode. W83877ATF/W83877ATG BIT NUMBER Data RX Data RX Data Bit 1 Bit 2 ...
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... If MSBE is set to a logical 1, and data length bits, two stop bits are sent and checked. Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in each serial character. W83877ATF/W83877ATG Data length select bit 0 (DLS0) ...
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... Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. W83877ATF/W83877ATG DLS0 0 1 ...
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... Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally connected to the modem control input RI . Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS . Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR . W83877ATF/W83877ATG ...
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... Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read by the CPU. Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU. Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read by the CPU. W83877ATF/W83877ATG ...
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... Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of UFR are programmed. W83877ATF/W83877ATG ...
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... First Second Second Third Fourth ** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1. W83877ATF/W83877ATG INTERRUPT SET AND FUNCTION Interrupt Source Interrupt Type - - No Interrupt pending 1. OER = 1 UART Receive Status 3. NSER = 1 1. RBR data ready RBR Data Ready 2. FIFO interrupt active level ...
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... The table below illustrates the use of the baud generator with a frequency of 1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed mode, the data transmission rate can be as high as 1.5M bps. W83877ATF/W83877ATG ...
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... Note 1: Only use in high speed mode, when FASTA/FASTB bits are set (refer to CR19 bit1 and CR19 bit0). Note 2 : Only use in high speed mode, when TURA/TURB bits are set (refer to CR0C bit7 and bit6). ** The percentage error for all baud rates, except where indicated otherwise, is 0.16% W83877ATF/W83877ATG DECIMAL DIVISOR USED TO GENERATE 16X CLOCK ...
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... Sets. The structure of he Register Sets is shown below. Reg 7 Reg 6 Reg 5 Reg 4 BDL/SSR Reg 2 Reg 1 Reg 0 Set 0 *Set 0, 1 are legacy/Advanced UART Registers *Set 2~7 are Advanced UART Registers W83877ATF/W83877ATG Set 1 Set 2 Set 3 Set 4 Set 5 Set 6 Set All in one Reg to Select SSR Publication Release Date:November 2006 ...
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... D_CHSW (DMA Channel Swap, in Set2.Reg2.Bit3) is set and the TX/RX DMA channel is swapped. Note that two DMA channels are defined in config register CR2A, which selects DMA channel or disables DMA channel DMA channel is enabled and TX DMA channel is disabled, then the single DMA channel will be selected. W83877ATF/W83877ATG SETS DESCRIPTION Counter REGISTER DESCRIPTION ...
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... Write to 1 enable USR interrupt or enable transmitter underrun interrupt. Bit 1: ETBREI - Enable TBR (Transmitter Buffer Register) Empty Interrupt Write to 1 enable transmitter buffer register empty interrupt. Bit 0: ERBRI - Enable RDR (Receiver Buffer Register) Interrupt Write to 1 enable receiver buffer register interrupt. W83877ATF/W83877ATG EHSRI ...
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... Set to 1 when (1) a frame has a grace end to be detected where the frame signal is defined in the physical layer of IrDA version 1.1 (2) abort signal or illegal signal has been detected during receiving valid data. Clear to 0 when this register is read. Remote Controller mode: Not used. W83877ATF/W83877ATG ...
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... Note that the FIFO Size is referred to SET2.Reg4. Bit 5, 4: TXFTL1 Transmitter FIFO Threshold Level To determine the TXTH_I (Transmitter Threshold Level Interrupt) is set to 1 when the Transmitter Threshold Level is less than the programmed value shown as follows. W83877ATF/W83877ATG BIT 5 BIT 4 BIT TXFTL1 ...
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... UART Control Register: Defined legacy UART. 6.3.2.5. Set0.Reg4 - Handshake Control Register (HCR) MODE B7 B6 Legacy 0 0 UART Advanced AD_MD2 AD_MD1 AD_MD0 SIR_PLS UART 0 0 Reset Value W83877ATF/W83877ATG TX FIFO Threshold Level ( FIFO Size: 16-byte Hex Value × × × － － 0 ...
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... If this bit sets to 1, the transmitter will wait for TX FIFO to reach threshold level or transmitter time-out which avoids short data bytes to want to transmit, before beginning to transmit data from TX FIFO. This is in order to avoid Underrun. Other modes: Not used. W83877ATF/W83877ATG SELECTED MODE Advanced UART Low speed MIR (0.576M bps) Advanced ASK-IR Advanced SIR High Speed MIR (1 ...
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... MIR, FIR modes: PHY_ERR - Physical Layer Error Set to 1 when an illegal data symbol is received, where the illegal data symbol is defined in physical layer of IrDA version 1.1. When this bit is set to 1, the decoder of receiver will be aborted, and a frame end signal is set to 1. W83877ATF/W83877ATG TBRE ...
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... MIR/FIR mode operated in DMA function switches to SIR mode. Bit 6 MIR, FIR modes: UNDRN - Underrun Set to 1 when transmitter is empty and not set S_FEND (in this register bit 3) operated in PIO mode or not TC (Terminal Count) operated in DMA mode. Clear to 0 when write to 1. W83877ATF/W83877ATG DSR CTS ...
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... Set to 1 that indicates one or more than one frame end still stay in receiver FIFO. Bit 0: MIR, FIR, Remote IR modes: RX_TO - Receiver FIFO or Frame Status FIFO time-out Set to 1 when receiver FIFO or frame status FIFO occurs time-out W83877ATF/W83877ATG An Entire Frame = Write Frame Data (First) + Write S_FEND (Last ...
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... Set 4.Reg 3 Note that DIS_BACK=1 (Disable Backward operation) in legacy UART/SIR/ASK-IR mode will not affect any register which can operate legacy SIR/ASK-IR. 6.3.3.2. Set1.Reg 2~7 These registers are defined the same as the Set 0 registers. W83877ATF/W83877ATG REGISTER DESCRIPTION Advanced Mode DIS_BACK=× Bit 7~5 ...
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... Setting this bit can check output data with internal data. Bit 4: D_CHSW - DMA TX/RX Channel Swap If using signal DMA channel in MIR/FIR mode, then the DMA channel can be swapped. D_CHSW Write to 1 enables output data during the ALOOP=1. W83877ATF/W83877ATG REGISTER DESCRIPTION BIT 5 BIT 4 BIT 3 EN_LOUT D_CHSW ...
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... DIS_BACK - Disable Backward Operation Write to 1, read or write BLL or BHL (Baud rate Divisor Latch Register, in Set1.Reg0~1), will disable backward legacy UART mode. When using legacy SIR/ASK-IR mode, this bit should be set avoid backward operation. Bit 6: Reserved, write 0. W83877ATF/W83877ATG TX FIFO THRESHOLD 16-Byte 32-Byte 13 23 Function Description DMA request (DREQ) is forced inactive after 10 ...
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... These bits setup transmitter FIFO size when FIFO is enabled. TX_FSZ1 6.3.4.5. Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only) MODE BIT 7 BIT 6 Advanced 0 0 UART 0 0 Reset Value W83877ATF/W83877ATG PRE-DIVISOR 13.0 1.625 6 FIFO SIZE 16 -Byte 32 -Byte Reserved TX FIFO SIZE 16 -Byte 32 -Byte Reserved BIT 5 BIT 4 ...
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... Reserved 6.3.5.1. Reg0 - Advanced UART ID (AUID) This register is read only. Indicates advanced UART version ID. Read it and return 1X 6.3.5.2. Reg1 - Mapped UART Control Register (MP_UCR) Read only. Reading this register that returns UART Control Register value of Set 0. W83877ATF/W83877ATG BIT 5 BIT 4 BIT 3 RXFD5 ...
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... When the counter down counts to zero, a new initial value will be re-loaded into timer counter. 6.3.6.2. Set4.Reg2 - Infrared mode Select (IR_MSL) MODE BIT 7 BIT 6 Advanced - - UART 0 0 Reset Value W83877ATF/W83877ATG . Write it to select other register Set. 16 BIT 5 BIT 4 BIT 3 SSR5 SSR4 SSR3 ...
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... Value 6.3.6.4. Set4.Reg4 Transmitter Frame Length (TFRLL/TFRLH) REG. BIT 7 BIT 6 TFRLL bit 7 bit Reset Value TFRLH - - - - Reset Value W83877ATF/W83877ATG OPERATION MODE SELECTED . A write to this register selects other Set. 16 BIT 5 BIT 4 BIT 3 SSR5 SSR4 SSR3 BIT 5 BIT 4 BIT 3 bit 5 bit 4 bit3 ...
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... Receiver Frame Length FIFO High Byte 6.3.7.1. Set5.Reg0 Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL) If flow control occurs from MIR/FIR mode change to SIR mode, then the pre-programming baud rate of FCBLL/FCBHL is loaded to advanced baud rate divisor latch (ADBLL/ADBHL). W83877ATF/W83877ATG BIT 5 BIT 4 BIT 3 ...
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... Set5.Reg3 - Sets Select Register (SSR) A write to this register will change Set of register. Reading this register will return EC REG. BIT 7 BIT 6 SSR SSR7 SSR6 1 1 default Value W83877ATF/W83877ATG BIT 5 BIT 4 BIT 3 - FC_DSW Next Mode After Flow Control Occurred Receiver Channel Transmitter Channel ...
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... Set5.Reg5 - Frame Status FIFO Register (FS_FO) This register are indicated the FIFO bottom of frame status. REG. BIT 7 BIT 6 FS_FO FSFDR LST_FR 0 0 Reset Value W83877ATF/W83877ATG BIT 5 BIT 4 BIT 3 FEND_M AUX_RX - STATUS FIFO THRESHOLD LEVEL BIT 5 BIT 4 BIT 3 ...
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... Reset Value Receiver Frame Length FIFO (RFLFL/RFLFH): These registers are 13-bit. Reading these registers will return received frame length. When read the register of RFLFH will pop-up another frame status and frame length if FSFDR=1 (Set5.Reg4.Bit7). W83877ATF/W83877ATG BIT 5 BIT 4 BIT 3 Bit 5 Bit 4 ...
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... This register config ASK-IR, MIR, FIR operation function. REG. BIT 7 BIT 6 IR_CFG2 SHMD_N SHDM_N FIR_CRC MIR_CRC 0 0 Reset Value Bit 7: SHMD_N - ASK-IR Modulation Disable SHMD_N Bit 6: SHDM_N - ASK-IR Demodulation Disable SHDM_N W83877ATF/W83877ATG REGISTER DESCRIPTION BIT 5 BIT 4 BIT Modulation Mode 0 SOUT modulate 500K Hz Square Wave 1 Demodulation Mode 0 Demodulation 500K Hz ...
Page 76
... Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width REG. BIT 7 BIT 6 MIR_PW - - 0 0 Reset Value This 5-bit register is set MIR output pulse width. M_PW4~0 00000 00001 00010 ... k 10 ... 11111 W83877ATF/W83877ATG BIT 5 BIT 4 BIT 3 - M_PW4 M_PW3 0 0 MIR Pulse Width (1.152M bps 20.83 ns 41.66 (==20.83*2) ns ... 20.83*k ...
Page 77
... M_FG3~0 - MIR beginning Flag Number These bits define the number of transmitter Start Flag of MIR. Note that the number of MIR start flag should be equal to or more than two which is defined in IrDA 1.1 physical layer. The default value is 2. W83877ATF/W83877ATG BIT 5 BIT 4 BIT 3 ...
Page 78
... FIR start flag should be equal to sixteen which is defined in IrDA 1.1 physical layer. The default value is 16. M_FG3~0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 W83877ATF/W83877ATG BEGINNING FLAG NUMBER Reserved 1 2 (Default Reserved BEGINNING FLAG NUMBER ...
Page 79
... Bit 4~0: RX_FSL4~0 - Receiver Frequency Select 4~0. Select the receiver operation frequency. W83877ATF/W83877ATG REGISTER DESCRIPTION BIT 5 BIT 4 BIT 3 RX_FR0 RX_FSL4 RX_FSL3 RX_FSL2 RX_FSL1 RX_FSL0 ...
Page 80
... Note: that the other non-defined values are reserved. Table: High Frequency range select of receiver RX_FSL4~0 00011 01000 01011 Note that the other non-defined values are reserved. W83877ATF/W83877ATG RX_FR2~0 (LOW FREQUENCY) 010 MAX. MIN. MAX. 29.6 24.7 31.7 32.0 26 ...
Page 81
... Note that the other non-defined TX_PW are reserved. Bit 4~0: TX_FSL4~0 - Transmitter Frequency Select 4~0. Selects the transmission frequency. Table: Low frequency selected. TX_FSL4~0 00011 00100 ... 11101 Note that the other non-defined TX_FSL4~0 are reserved. W83877ATF/W83877ATG RX_FSL4~0 (SHARP ASK-IR) 010 011 100 BIT 5 BIT 4 BIT LOW FREQUENCY μ ...
Page 82
... Write to 0 causes T-period sampling to be used, so that the T-period is programmed UART baud rate. Write to 1 causes direct use of programmed baud rate to do over-sampling. Bit 5: RXCFS - Receiver Carry Frequency Select RXCFS 0 1 Bit 4: Reserved, write 0. W83877ATF/W83877ATG BIT 5 BIT 4 BIT 3 RXCFS - TX_CFS 0 0 (Number of bits ...
Page 83
... REG. BIT 7 BIT 6 IRM_SL1 IR_MSP SIR_SL2 SIR_SL1 SIR_SL0 0 0 default Value W83877ATF/W83877ATG Selected Frequency 30K ~ 56K Hz 400K ~ 480K Hz Demodulation Mode Enables internal decoder Disables internal decoder TX Modulation Mode Continuously sends pulse for logic 0 8 pulses for logic 0 and no pulse for logic 1. ...
Page 84
... These bits setup the MIR operational mode when AM_FMT=1 and AD_MD2~0 set to MIR mode. These values will be automatically loaded to IR_SL2~0, respectively. 6.3.9.7. Set7.Reg6 - Infrared module (Front End) Select 3 (IRM_SL3) REG. BIT 7 BIT 6 IRM_SL3 - LRC_SL2 LRC_SL1 LRC_SL0 0 0 default Value W83877ATF/W83877ATG BIT 5 BIT 4 BIT 3 FIR_SL1 FIR_SL0 - BIT 5 BIT 4 ...
Page 85
... If the IR module has only one receiving path, then this bit should be set to 0. IRX_MSL Bit 5: IRSL0D - Direction of IRSL0 Pin Select function for IRRXH or IRSL0 because they share a common pin with different input/output direction. IRSL0_D W83877ATF/W83877ATG BIT 5 BIT 4 BIT 3 IRSL0D RXINV TXINV 0 ...
Page 86
... FIR (4M bps), (3) IRRX is the input of the low speed or high speed IR receiver, IRRXH is the input of the high speed IR receiver. Bit 4: RXINV - Receiving Signal Invert Write to 1 inverts the receiving signal. Bit 3: TXINV - Transmitting Signal Invert Write to 1 inverts the transmitting signal. Bit 2~0: Reserved, write 0. W83877ATF/W83877ATG AUX_RX HIGH SPEED ...
Page 87
... CONNECTOR OF W83877ATF 1 19 2-9 9-14,16- Notes: n<name > : Active Low 1. Compatible Mode 2. High Speed Mode 3. For more information, refer to the IEEE 1284 standard. W83877ATF/W83877ATG PIN SPP EPP ATTRIBUTE O nSTB nWrite I/O PD<0:7> PD<0:7> I nACK I BUSY nWait SLCT Select O nAFD nDStrb I nERR nError ...
Page 88
... TABLE 4-1-B Parallel Port Connector and Pin Definition for EXTFDD and EXT2FDD Modes HOST PIN NUMBER CONNECTOR OF W83877ATF W83877ATF/W83877ATG PIN PIN SPP ATTRIBUTE ATTRIBUTE O nSTB --- I/O PD0 I I/O PD1 I I/O PD2 I I/O PD3 I I/O PD4 I I/O PD5 --- I/O PD6 OD I/O PD7 OD I nACK OD I BUSY OD ...
Page 89
... Bit 6: This bit represents the current state of the printer's ACK signal means the printer has received a character and is ready to accept another. Normally, this signal will be active for approximately 5 microseconds before BUSY stops. Bit means the printer has detected the end of paper. W83877ATF/W83877ATG A0 REGISTER 0 ...
Page 90
... Bit starts the printer (50 microsecond pulse, minimum). Bit causes the printer to line-feed after a line is printed. Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse. W83877ATF/W83877ATG ...
Page 91
... IOW latches the data for the duration of the EPP write cycle. During a read operation, ports PD0-PD7 are read, and the leading edge of IOR causes an EPP read cycle to be performed and the data to be output to the host CPU. W83877ATF/W83877ATG ...
Page 92
... This signal is active low. It denotes a data read or write operation. nError I Error; same as SPP mode. This signal is active low. When it is active, the EPP device is reset to its nInits O initial operating mode. nAStrb O This signal is active low. It denotes an address read or write operation. W83877ATF/W83877ATG PD6 PD5 PD4 PE SLCT ACK ...
Page 93
... Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte repeated. The hardware support for compression is optional. For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard. W83877ATF/W83877ATG - 86 - ...
Page 94
... During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input. The contents of this register are output to the PD0-PD7 ports. During a read operation, ports PD0-PD7 are read and output to the host. The bit definitions are as follows: W83877ATF/W83877ATG I/O ECP MODES ...
Page 95
... Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input. Bit 2-0: These three bits are not implemented and are always logic one during a read. W83877ATF/W83877ATG ...
Page 96
... ECP parallel port protocol. Transfers to the FIFO are byte aligned. When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system. W83877ATF/W83877ATG ...
Page 97
... IRQ resources selected by PnP register (default) 001 IRQ7 010 IRQ9 011 IRQ10 100 IRQ11 101 IRQ14 110 IRQ15 111 IRQ5 Bit 2-0: These five bits are at high level during a read and can be written W83877ATF/W83877ATG IRQ resource - 90 - IRQx 0 IRQx 1 IRQx 2 ...
Page 98
... Disables the interrupt generated on the asserting edge of nFault. 0 Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted (interrupt) an interrupt will be generated and this bit is written from Bit 3: Read/Write 1 Enables DMA. 0 Disables DMA unconditionally. W83877ATF/W83877ATG Publication Release Date:November 2006 - 91 - Empty Full ...
Page 99
... MODE ecr Notes: 1. These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO. W83877ATF/W83877ATG PD5 PD4 PD3 Address or RLE field PError Select nFault Directio ackIntEn SelectIn Parallel Port Data FIFO ...
Page 100
... PError (nAckReverse) Select (Xflag) nAutoFd (HostAck) nFault (nPeriphRequest) nInit (nReverseRequest) nSelectIn (ECPMode) W83877ATF/W83877ATG The nStrobe registers data or address into the slave on the O asserting edge during write operations. This signal handshakes with Busy. These signals contains address or data or RLE data. This signal indicates valid data driven by the peripheral when I asserted ...
Page 101
... The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled. W83877ATF/W83877ATG - 94 - ...
Page 102
... Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive. W83877ATF/W83877ATG Publication Release Date:November 2006 - 95 - Version 1.0 ...
Page 103
... The PnP feature is implemented through a set of Extended Function Registers (CR20 to 29). Details on configuring these registers are given in Section 8. The default values of these PnP-related registers set the system to a configuration compatible with environments designed with previous Winbond I/O chips. W83877ATF/W83877ATG - 96 - ...
Page 104
... W83877ATF/ATG enters the powerdown mode as soon as it expires. Once any device is awakened, the global stand-by is also awakened. The initial count values of the devices are held in the configuration registers CR35 to CR39. W83877ATF/W83877ATG Publication Release Date:November 2006 - 97 - ...
Page 105
... Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. 2. There may be none, one or more Idle states during the Stop Frame. 3. The next IRQSER cycle's Start Frame pulse may or may not start immediately after the turn-around clock of the Stip Frame. W83877ATF/W83877ATG IRQ0 FRAME R ...
Page 106
... If the corresponding IRQ is inactive, then IRQSER must be left tri-stated. During the Recovery phase, the peripheral device drives the IRQSER high. During the Turn-around phase, the peripheral device left the IRQSER tri-stated. The IRQ/Data Frame has a number of specific order, as shown in Table 7-1. W83877ATF/W83877ATG Publication Release Date:November 2006 - 99 - Version 1.0 ...
Page 107
... Table 7-1 IRQSER Sampling periods IRQ/DATA FRAME 32:22 W83877ATF/W83877ATG SIGNAL SAMPLED # OF CLOCKS PAST START IRQ0 IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK INTA INTB INTC INTD Unassigned - 100 - ...
Page 108
... IRQSER cycle is performed. For IRQSER system suspend, insertion, or removal application, the Host controller should be programmed into Continuous(Idle) mode first. This is to guarantee IRQSER bus in the Idle state before the system configuration changes. W83877ATF/W83877ATG Publication Release Date:November 2006 - 101 - Version 1.0 ...
Page 109
... Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers PC/AT system, their port addresses are 250H or 3F0H (as described in the above section). W83877ATF/W83877ATG ADDRESS AND VALUE write 88H to the location 250H ...
Page 110
... Bit 7-bit 4: Reserved. PRTMOD1 PRTMOD0 (Bit 3, 2): These two bits and PRTMOD2 (CR9 bit 7) determine the parallel port mode of the W83877ATF/ATG (as shown in the following Table 8-1). Table 8-1 PRTMODS2 PRTMODS1 (BIT 7 OF CR9) (BIT 3 OF CR0 W83877ATF/W83877ATG PRTMODS0 (BIT 2 OF CR0 ...
Page 111
... When the device is in Extended Function mode and EFIR is 01H, the CR1 register can be accessed through EFDR. The bit definitions are as follows: 7 ABCHG (Bit 7): This bit enables the FDC AB Change Mode. Default to be enabled at power-on reset. 0 Drives A and B assigned as usual 1 Drive A and drive B assignments exchanged Bit 6-bit 0: Reserved. W83877ATF/W83877ATG 104 - reserved ...
Page 112
... Disables MIDI support, UARTA clock = 24 MHz divided by 13 (default) 1 Enables MIDI support, UARTA clock = 24 MHz divided by 12 SUBMIDI (Bit 0): This bit selects the clock divide rate of UARTB. 0 Disables MIDI support, UARTB clock = 24 MHz divided by 13 (default) 1 Dnables MIDI support, UARTB clock = 24 MHz divided by 12 W83877ATF/W83877ATG Publication Release Date:November 2006 ...
Page 113
... The output pins of UARTA will be tri-stated when UARTA is in power-down mode. URBTRI (Bit 0): This bit enables or disables the tri-state outputs of UARTB in power-down mode. 0 The output pins of UARTB will not be tri-stated when UARTB is in power-down mode. 1 The output pins of UARTB will be tri-stated when UARTB is in power-down mode. W83877ATF/W83877ATG ...
Page 114
... EFDR. The bit definitions are as follows: 7 Bit 7- bit 6: Reserved SEL4FDD (Bit 5): Selects four FDD mode 0 Selects two FDD mode (default, see Table 8-2) 1 Selects four FDD mode DSA , DSB , MOA and MOB output pins are encoded as show in Table 8-3 to select four drives. W83877ATF/W83877ATG ...
Page 115
... This bit enables or disables the tri-state outputs of the FDC in power-down mode. 0 The output pins of the FDC will not be tri-stated when FDC is in power-down mode. 1 The output pins of the FDC will be tri-stated when FDC is in power-down mode. Bit 0: Reserved. W83877ATF/W83877ATG MOB MOA Bit 1 Bit 0 0 ...
Page 116
... Selects normal mode. When RWC = 0, the data transfer rate is 250 Kb/s. When RWC = 1, the data transfer rate is 500 Kb/s. Three mode FDD select (EN3MODE = 1): 01 RWC = 0, selects 1.2 MB high-density FDD. 10 RWC = 1, selects 1.44 MB high-density FDD. 11 Don't care RWC , selects 720 KB double-density FDD. W83877ATF/W83877ATG FDD A type 0 ...
Page 117
... If the diskette is removed from the disk drive and inserted again, however, typing the DIR command will reveal that the contents of the diskette have not been modified and the diskette was not actually reformatted. W83877ATF/W83877ATG , selects 720 KB double-density FDD. 6 ...
Page 118
... This bit and PRTMODS1, PRTMODS0 (bits CR0) select the operating mode of the W83877ATF. Refer to the descriptions of CR0. LOCKREG (Bit 6): This bit enables or disables the reading and writing of all configuration registers. 0 Enables the reading and writing of CR0-CR45 1 Disables the reading and writing of CR0-CR45 (locks W83877ATF extension functions) EN3MODE (Bit 5): W83877ATF/W83877ATG CHIP ID0 ...
Page 119
... When the device is in Extended Function mode and EFIR is 0AH, the CRA register can be accessed through EFDR. This register is reserved. 11.2.12 Configuration Register B (CR0B), default = 0CH When the device is in Extended Function mode and EFIR is 0BH, the CRB register can be accessed through EFDR. The bit definitions are as follows: W83877ATF/W83877ATG RWC Normal 0 1 ...
Page 120
... This bit determines the polarity of all FDD interface signals. 0 FDD interface signals are active low 1 FDD interface signals are active high DRV2EN (Bit 0): PS/2 mode only When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A. W83877ATF/W83877ATG MFM 0 Model 30 mode 1 PS/2 mode 0 ...
Page 121
... SINB pin of UART B function or IRRX pin of IR function in normal condition. 1 inverse the SINB pin of UART B function or IRRX pin of IR function TX2INV (Bit 0): 0 the SOUTB pin of UART B function or IRTX pin of IR function in normal condition. 1 inverse the SOUTB pin of UART B function or IRTX pin of IR function. W83877ATF/W83877ATG ...
Page 122
... SIRRX0 (Bit 4): IRRX pin selection bit 0 SIRRX1 HDUPLX (Bit 3): 0 The IR function is Full Duplex. 1 The IR function is Half Duplex. IRMODE2 (Bit 2): IR function mode selection bit 2 IRMODE1 (Bit 1): IR function mode selection bit 1 IRMODE0 (Bit 0): IR function mode selection bit 0 W83877ATF/W83877ATG SIRTX0 0 disabled 1 IRTX1 (pin 43) ...
Page 123
... IRDA Mod. Mod1.6u 500KHZ 11.2.15 Configuration Register E (CR0E), Configuration Register F (CR0F) Reserved for testing. Should be kept all 0's. W83877ATF/W83877ATG IRTX tri-state Active pulse 1.6 μ S Active pulse 3/16 bit time Inverting IRTX pin Inverting IRTX & 500 KHZ clock Inverting IRTX Inverting IRTX & ...
Page 124
... When the device is in Extended Function mode and EFIR is 11H, the CR11 register can be accessed through EFDR. The bit definitions are as follows: G0CADM1-G0CADM0 (Bit 7, 6): GIOP0 address bit compare mode selection G0CADM1 G0CADM0 Bit 5-bit 3: Reserved GIO0AD10-GIO0AD8 (Bit 2-bit 0): GIOP0 (pin 92) address bit 10-bit 8. W83877ATF/W83877ATG ...
Page 125
... When the device is in Extended Function mode and EFIR is 13H, the CR13 register can be accessed through EFDR. The bit definitions are as follows: G1CADM1-G1CADM0 (bit 7, 6): GIOP1 address bit compare mode selection G1CADM1 G1CADM0 Bit 5- bit 3: Reserved GIO1AD10-GIO1AD8 (Bit 2-bit 0): GIOP1 (pin 96) address bit 10-bit 8. W83877ATF/W83877ATG ...
Page 126
... X GIO0CSH(Bit 4): the Chip Select pin will be active LOW when (AEN = L) AND (SA10-0 = GIO0AD10 (NIOR = L) OR (NIOW = L) the Chip Select pin will be active HIGH when (AEN = L) AND (SA10 GIO0AD10-0) OR (NIOR = L) OR (NIOW = L) GCS0IOR (Bit 3): See below. W83877ATF/W83877ATG GIOP0MD0 inactive (tri-state data output pin (SD0 → GIOP0), when (AEN = L) ...
Page 127
... GIOP0 functions as a data pin, and inverse GIOP0 → SD0, inverse 1 1 SD0 → GIOP0 11.2.21 Configuration Register 15 (CR15), default = 00H When the device is in Extended Function mode and EFIR is 15H, the CR15 register can be accessed through EFDR. The bit definitions are as follows: 7 W83877ATF/W83877ATG 120 - ...
Page 128
... GCS1IOW GDA0OPI (Bit 1): See below. W83877ATF/W83877ATG GIOP1MD0 0 inactive (tri-state data output pin (SD1 → GIOP1), when (AEN = L) 1 AND (NIOW = L) AND (SA10-0 = GIO1AD10-0), the value of SD1 will be present on GIOP1 as a data input pin (GIOP1 → SD1), when (AEN = L) 0 AND (NIOR = L) AND (SA10-0 = GIO1AD10-0), the value of GIOP1 will be present on SD1 as a data input/output pin (GIOP1 ↔ ...
Page 129
... PnP-related registers (CR20, CR23-29) reset to be all 0s. 1 default settings for these registers. W83877ATF/W83877ATG GIOP1 functions as a data pin, and GIOP1 → SD1, SD1 → GIOP1 GIOP1 functions as a data pin, and inverse GIOP1 → SD1, SD1 → GIOP1 GIOP1 functions as a data pin, and GIOP1 → SD1, inverse SD1 → ...
Page 130
... When the device is in Extended Function mode and EFIR is 17H, the CR17 register can be accessed through EFDR. The bit definitions are as follows: 7 Bit 7-bit 5: Reserved. PRIRQOD (Bit 4): 0 printer IRQ ports are totem-poles in SPP mode and open-drains in ECP/EPP mode. 1 printer IRQ ports are totem-poles in all modes. W83877ATF/W83877ATG PNPCVS = 1 FCH DEH FEH BEH 23H 05H 43H ...
Page 131
... EFDR. The bit definitions are as follows: 7 This register is used to select whether these interrupt request pins are in the IRQ sharing mode. While in the IRQ sharing mode, the corresponding pin is low active for 200ns for the interrupt request and keeps tri-stated otherwise. W83877ATF/W83877ATG ...
Page 132
... IRQ_C in the IRQ sharing mode. SHARB(Bit 1): 0 pin IRQ_B in the legacy ISA IRQ mode. 1 pin IRQ_B in the IRQ sharing mode. SHARA (Bit 0): 0 pin IRQ_A in the legacy ISA IRQ mode. 1 pin IRQ_A in the IRQ sharing mode. W83877ATF/W83877ATG Publication Release Date:November 2006 - 125 - Version 1.0 ...
Page 133
... This register is used to select the base address of the Floppy Disk Controller (FDC) from 100H-3F0H on 16-byte boundaries. NCS = 0 and A10 = 0 are required to access the FDC registers. A[3:0] are always decoded as 0xxxb. FDCAD7-FDCAD2 (Bit 7-bit 2): match A[9:4]. Bit and bit disable this decode. Bit 1-bit 0: Reserved, fixed at zero. W83877ATF/W83877ATG ...
Page 134
... This register is used to select the base address of the UART A from 100H-3F8H on 8-byte boundaries. NCS = 0 and A10 = 0 are required to access the UART A registers. A[2:0] are don't-care conditions. URAAD7-URAAD1 (Bit 7-bit 1): match A[9:3]. Bit and bit disable this decode. Bit 0: Reserved, fixed at zero. W83877ATF/W83877ATG ...
Page 135
... When the device is in Extended Function mode and EFIR is 26H, the CR26 register can be accessed through EFDR. Default = 23H if CR16 bit default = 00H if CR16 bit The bit definitions are as follows: 7 FDCDQS3-FDCDQS0 (Bit 7-bit 4): Allocate DMA resource for FDC. PRTDQS3-PRTDQS0 (Bit 3-bit 0): Allocate DMA resource for PRT. BIT 7- BIT4, BIT 3 - BIT 0 0000 0001 0010 0011 W83877ATF/W83877ATG ...
Page 136
... CR27[7:5] 000 reflect other IRQ resources selected by CR27[3:0] (default) 001 IRQ 7 010 IRQ 9 011 IRQ 10 100 IRQ 11 101 IRQ 14 110 IRQ 15 111 IRQ 5 Bit 4: Reserved. W83877ATF/W83877ATG IRQ RESOURCE - 129 - 0 PRTIQS0 PRTIQS1 PRTIQS2 PRTIQS3 reserved ECPIRQx0 ECPIRQx1 ECPIRQx2 Publication Release Date:November 2006 ...
Page 137
... CR27[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 W83877ATF/W83877ATG SELECT IRQ PIN None IRQ_A IRQ_B IRQ_C IRQ_D IRQ_E IRQ_F IRQ_G IRQ_H IRQ/DATA FRAME PERIOD None IRQ1 Reserved for SMI IRQ3 IRQ4 IRQ5 ...
Page 138
... FDCIQS3-FDCIQS0 (Bit 7-bit 4): Allocate interrupt resource for FDC. IQNIQS3-IQNIQS0 (Bit 3-bit 0): Allocate interrupt resource for IRQIN. 11.2.34 Configuration Registers (CR2A) When the device is in Extended Function mode and EFIR is 2AH, the CR2A register can be accessed through EFDR. This register default value W83877ATF/W83877ATG ...
Page 139
... When the device is in Extended Function mode and EFIR is 2BH, the CR2B register can be accessed through EFDR. This register default value Bit 7~6: PIN1FUN1~0 - Pin 1 function select. * IRQMODS Note that: IRQMODS is defined in CR31.Bit2, that is, the IRQ mode selection bit. Bit 5-4: PIN2FUN1~0 - Pin 2 function select. PIN2FUN1 W83877ATF/W83877ATG . The bit definitions are as follows PIN1FUN1 PIN1FUN0 PIN2FUN0 0 ...
Page 140
... X * Note that the bit IRQMODS is defined in CR31.Bit2, that is, a IRQ mode selection. Note: The IRSL0/IRRXH selection is determined by Bit 5(IRSL0 Mode selection) of Register7 of Bank7. When setting Bit 5 to logical 1, IRSL0 is selected; When setting Bit 5 to logical 0, IRRXH is selected. W83877ATF/W83877ATG PIN3FUN0 PIN93FUN1 The bit definitions are as follows: ...
Page 141
... This register controls the data rate selection for FDC. It also controls if precompensation is enabled. DRTA1, DRTA0 (bit 1 - bit 0): These two bits combining with data rate selection bits in Date Rate Register select the operational data rate for FDD A as follows: W83877ATF/W83877ATG 16 . The bit definitions are as follows: 16 ...
Page 142
... These two bits combining with data rate selection bits in Date Rate Register select the operational data rate for FDD B as shown in last table. DIS_PRECOMP1 (bit 5): This bit controls if precompensation is enabled for FDD B. 0 enable precompensation for FDD B 1 disable precompensation for FDD B Bit 7 - bit 6: Rreserved. W83877ATF/W83877ATG DATA RATE DRATE1 DRATE0 ...
Page 143
... DIS_BST(Bit3): Disable FDC DMA Burst Mode. 0 Enable FDC burst mode. (Default) 1 Disable FDC burst mode. 11.2.39 Configuration Register 31 (CR31), default=00H When the device is in Extended Function mode and EFIR is 31H, the CR31 register can be accessed through EFDR. The bit definitions are as follows: 7 W83877ATF/W83877ATG ...
Page 144
... Bit 3: Reserved. W83877ATF/W83877ATG MAPPED IRQ PIN IRQ/DATA FRAME PERIOD None IRQ1 Reserved for SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 ...
Page 145
... CHIPPME(CR32 bit 7) are both set to 1. FDCPME (Bit 2): FDC power management enable. 0 disable the auto power management function. 1 enable the auto power management function, if this bit and CHIPPME(CR32 bit 7) are both set to 1. W83877ATF/W83877ATG 138 - ...
Page 146
... PM1a_CNT_BLK is equal to PM1a_EVT_BLK + 4, and PM_TMR_BLK is equal to PM1a_EVT_BLK + 8. Bit 1 - bit 0: Reserved, fixed at 0. 11.2.42 Configuration Register 34 (CR34), default=00H When the device is in Extended Function mode and EFIR is 34H, the CR34 register can be accessed through EFDR. The bit definitions are as follows: 7 W83877ATF/W83877ATG 11,1111,0000 ,i ...
Page 147
... URAPME=1 (CR32 bit 1), (2). If the register is set to 00H, UART A will remain in the current state (working or sleeping). 11.2.44 Configuration Register 36 (CR36), default=00H When the device is in Extended Function mode and EFIR is 36H, the CR36 register can be accessed through EFDR. The bit definitions are as follows: 7 W83877ATF/W83877ATG ,i.e., 100H ~ 3F8H, where bit 0 of the base address ...
Page 148
... The time resolution of this value is minute or second, which is defined by the TMIN_SEL bit of the CR3A. Note that (1). This register is valid only when the power management function of FDC is enabled, that is, CHIPPME=1 (CR32 bit 7) and FDCPME=1 (CR32 bit 2), (2). If the register is set to 00H, FDC will remain in the current state (working or sleeping). W83877ATF/W83877ATG ...
Page 149
... If this register is set to 0, the power down function will be invalid. The time resolution of this register value is minute or second, which is defined by the TMIN_SEL bit of CR3A. Note that (1). This register is valid when the CHIPPME = 1 (CR32 bit 7), and (2) If the register is set to 00H, W83877ATF/ATG chip will remain in the current state (working or sleeping). W83877ATF/W83877ATG ...
Page 150
... IRQSER pin. 11.2.49 Configuration Register 3B (CR3B), default=00H Reserved for testing. Should be kept all 0's. 11.2.50 Configuration Register 40 (CR40), default=00H When the device is in Extended Function mode and EFIR is 40H, the CR40 register can be accessed through EFDR. The bit definitions are as follows: W83877ATF/W83877ATG ...
Page 151
... URBIDLSTS (Bit 0): UART B idle status. 0 UART B is now in the working state. 1 UART B is now in the sleeping state due to no UART B access, no IRQ, the receiver is now waiting for a start bit, the transmitter shift register is now empty, and no transition on MODEM control input lines. W83877ATF/W83877ATG ...
Page 152
... URBTRAPSTS (Bit 0): UART B trap status. 0 UART B is now in the sleeping state. 1 UART B is now in the working state due to any UART B access, any IRQ, the receiver begins receiving a start bit, the transmitter shift register begins transmitting a start bit, and any transition on MODEM control input lines. W83877ATF/W83877ATG ...
Page 153
... When the device is in Extended Function mode and EFIR is 43H, the CR43 register can be accessed through EFDR. This register is reserved. 11.2.54 Configuration Register 44 (CR44), default=00H When the device is in Extended Function mode and EFIR is 44H, the CR44 register can be accessed through EFDR. This register is reserved. W83877ATF/W83877ATG ...
Page 154
... SMI interrupt due to the UART A's IRQ. 1 enable the generation of an SMI interrupt due to the UART A's IRQ. URBIRQEN (Bit 0): 0 disable the generation of an SMI interrupt due to the UART B's IRQ. 1 enable the generation of an SMI interrupt due to the UART B's IRQ. W83877ATF/W83877ATG 147 - ...
Page 155
... GIO1AD7 GIO1AD6 CR13 0000 0000 G1CADM1 G1CADM0 CR14 0000 0000 GIOP0MD2 GIOP0MD1 CR15 0000 0000 GIOP1MD2 GIOP1MD1 1 CR16 00ss 0s0s 0 CR17 0000 0000 0 CR18 0000 0000 SHARH SHARG CR19 0000 0000 0 W83877ATF/W83877ATG PRTMODS1 EPPVER 0 0 URAPWD URBPWD PRTTRI ECPFTHR3 0 SEL4FDD FIPURDWN ...
Page 156
... CR45 0000 0000 0 Notes: 1. 's' means its value depends on corresponding power-on setting pin. 2. These default values are valid when CR16 bit during power-on reset; They will be all 0's if CR16 bit W83877ATF/W83877ATG FDCAD5 FDCAD4 FDCAD3 PRTAD5 PRTAD4 PRTAD3 URAAD5 URAAD4 ...
Page 157
... SCI interrupt is routed to pin SCI , which is dedicated for the SCI function. The other way to output the SCI interrupt is to route to one interrupt request signal pin IRQA~H, which is selected through CR31 bit[7:4]. Another way is output the SCI interrupt is to route to pin IRQSER. W83877ATF/W83877ATG SMI_EN IRQs ...
Page 158
... For the process of generating an interrupt from SMI to SCI or from SCI to SMI, see the following figure for an illustration. from SMI to SCI BIOS_RLS GBL_EN from SCI to SMI GBL_RLS BIOS_EN Bus Master SCI BM_CNTPL BM_RLD : Status bit : Enable bit W83877ATF/W83877ATG clear GBL_STS set To SCI Logic clear BIOS_STS set To SMI Logic clear BM_STS set To SCI Logic ...
Page 159
... The TMR_ON is located in GPE register block cleared to 0, the power management timer function will not work. There are no timer reset requirements, except that the timer should function after power-up. See the following figure for an illustration. TMR_ON 3.579545 MHz W83877ATF/W83877ATG TMR_STS 24 bit counter Bits (23-0) 24 ...
Page 160
... Power Management 1 Status Register 1 (PM1STS1) Register Location: <CR33> System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits 7 W83877ATF/W83877ATG to 11,1111,0000 ,i.e., 100H ~ 3F0H, where bit 1 and bit 11,1111,1000 ,i.e., 100H ~ 3F8H, where bit 0 of the base ...
Page 161
... WAK_STS sleeping/working state machine automatically upon the expiry of the global standby timer. Writing a 0 has no effect. Upon the WAK_STS beingcleared and all devices being in sleeping state, the whole chip enters the sleeping state. W83877ATF/W83877ATG DESCRIPTION ...
Page 162
... Reserved Reserved. 11.4.4 Power Management 1 Enable Register 2 (PM1EN2) Register Location: <CR33>+3H System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits 7 6 BIT NAME 0-7 Reserved Reserved. These bits always return a value of zero. W83877ATF/W83877ATG DESCRIPTION Reserved Reserved Reserved Reserved Reserved ...
Page 163
... Power Management 1 Control Register 2 (PM1CTL2) Register Location: <CR33>+5H System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits 7 6 BIT NAME 0-7 Reserved Reserved. These bits always return a value of zero. W83877ATF/W83877ATG SCI_EN BM_RLD GBL_RLD Reserved Reserved Reserved Reserved Reserved DESCRIPTION ...
Page 164
... Reserved. These bits always return a value of zero. 11.4.8 Power Management 1 Control Register 4 (PM1CTL4) Register Location: <CR33>+7H System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits 7 6 BIT NAME 0-7 Reserved Reserved. These bits always return a value of zero. W83877ATF/W83877ATG DESCRIPTION DESCRIPTION Publication Release Date:November 2006 - 157 - ...
Page 165
... The TMR_STS bit is set any time the last bit of the timer (bit 23) goes from from the TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. 11.4.10 Power Management 1 Timer 2 (PM1TMR2) Register Location: <CR33>+9H System I/O Space Default Value: 00h Attribute: Read only Size: 8 bits 7 6 W83877ATF/W83877ATG DESCRIPTION 158 - ...
Page 166
... MR reset, then the counter will continue counting from where it stopped. The TMR_STS bit is set any time the last bit of the timer (bit 23) goes from from the TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. W83877ATF/W83877ATG DESCRIPTION 2 1 ...
Page 167
... UART B SCI status, which is set by the UART B IRQ. 1 URASCISTS UART A SCI status, which is set by the UART A IRQ. 2 FDCSCISTS FDC SCI status, which is set by the FDC IRQ. 3 PRTSCISTS PRT SCI status, which is set by the printer port IRQ. 4-7 Reserved Reserved. W83877ATF/W83877ATG DESCRIPTION ...
Page 168
... These bits are used to enable the device's IRQ sources onto the SCI logic. The SCI logic output for the IRQs is as follows: SCI logic output = (URBSCIEN and URBSCISTS) or (URASCIEN and URASCISTS) or (FDCSCIEN and FDCSCISTS) or (PRTSCIEN and PRTSCISTS) W83877ATF/W83877ATG DESCRIPTION ...
Page 169
... BIT NAME 0-7 Reserved Reserved. These bits always return a value of zero. 11.4.17 General Purpose Event 1 Status Register 1 (GP1STS1) Register Location: <CR34>+4H System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits 7 6 W83877ATF/W83877ATG DESCRIPTION DESCRIPTION 162 - Reserved Reserved Reserved Reserved ...
Page 170
... BIT NAME 0-7 Reserved Reserved. These bits always return a value of zero. 11.4.19 General Purpose Event 1 Enable Register 1 (GP1EN1) Register Location: <CR34>+6H System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits 7 W83877ATF/W83877ATG DESCRIPTION DESCRIPTION 163 - Reserved Reserved Reserved Reserved ...
Page 171
... This bit is used to set the BM_STS bit and if the BM_RLD bit is also set, then an SCI interrupt is generated. Writing a 1 sets BM_CNTRL to 1 and also 1 BM_CNTRL sets BM_STS. Writing a 0 has no effect. Writing BM_STS clears BM_STS and also clears BM_CNTRL. 2-7 Reserved Reserved. W83877ATF/W83877ATG DESCRIPTION DESCRIPTION ...
Page 172
... Power-On Register Address Reset Value GP0STS1 <CR34> 0000 0000 GP0STS2 <CR34>+1H 0000 0000 GP0EN1 <CR34>+2H 0000 0000 GP0EN2 <CR34>+3H 0000 0000 GP1STS1 <CR34>+4H 0000 0000 GP1STS2 <CR34>+5H 0000 0000 GP1EN1 <CR34>+6H 0000 0000 GP1EN2 <CR34>+7H 0000 0000 W83877ATF/W83877ATG GBL_STS BM_STS GBL_EN ...
Page 173
... Input High Leakage Input Low Leakage I/O - TTL level bi-directional pin with source-sink capabilities 24t Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage W83877ATF/W83877ATG RATING -0.5 to 7.0 -0 +70 -55 to +150 = 0V) SS SYM. MIN. ...
Page 174
... CMOS level input pin c Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage IN - CMOS level schmitt-triggered input pin cs Input Low Threshold Voltage Input High Threshold Voltage Hysteresis ( Input High Leakage Input Low Leakage W83877ATF/W83877ATG SYM. MIN. TYP. MAX ...
Page 175
... Data setup time to IOW ↑ Data hold time from IOW ↑ IRQ delay from IOW ↑ DRQ cycle time DRQ delay time DACK ↓ DRQ to DACK delay DACK width IOR delay from DRQ IOW delay from DRQ W83877ATF/W83877ATG TEST SYM. MIN. CONDITIONS ...
Page 176
... DIR setup time to STEP DIR hold time from STEP STEP pulse width STEP cycle width WD pulse width Write precompensation Notes: 1. Typical values for ° C and normal supply voltage. 2. Programmable from 2 mS through increments. W83877ATF/W83877ATG TEST SYM. CONDITIONS T MRW 135/220 T TC 1.8/3/3. ...
Page 177
... Parallel Port Mode Parameters PARAMETER PD0-7, INDEX , STROBE , AUTOFD Delay from IOW IRQ Delay from ACK , nFAULT IRQ Delay from IOW IRQ Active Low in ECP and EPP Modes ERROR Active to IRQ Active W83877ATF/W83877ATG TEST SYMBOL CONDITIONS T SINT T 100 pF Loading RINT ...
Page 178
... WAIT Asserted to PD Hi-Z Command Asserted to PD Valid Command Deasserted to PD Hi-Z WAIT Deasserted to PD Drive WRITE Deasserted to Command PBDIR Set to Command PD Hi-Z to Command Asserted Asserted to Command Asserted WAIT Deasserted to Command Deasserted Time out PD Valid to WAIT Deasserted PD Hi-Z to WAIT Deasserted W83877ATF/W83877ATG SYM. MIN ...
Page 179
... IOW Deasserted to WRITE Deasserted and PD invalid 12.3.6 Parallel Port FIFO Timing Parameters PARAMETER DATA Valid to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive BUSY Inactive to PD Inactive BUSY Inactive to nSTROBE Active nSTROBE Active to BUSY Active W83877ATF/W83877ATG SYM. MIN ...
Page 180
... Asserted to BUSY Asserted BUSY Asserted to nSTROBE Deasserted 12.3.8 ECP Parallel Port Reverse Timing Parameters PARAMETER PD Valid to nACK Asserted nAUTOFD Deasserted to PD Changed nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted nACK Deasserted to nAUTOFD Asserted PD Changed to nAUTOFD Deasserted W83877ATF/W83877ATG SYMBOL MIN. MAX ...
Page 181
... Processor Write Operation SA0-SA9 AEN TAW DACK IOW D0-D7 IRQ DMA Operation TAM DRQ DACK TMA TMRW IOW or IOR TMW (IOW) TMR (IOR) W83877ATF/W83877ATG TRA TRR TDH TDF TR TWA TWW TWD TDW TWI DIR TMCY TAA STEP - 174 - Write Date WD TWDD ...
Page 182
... INPUT DATA) IRQ3 or IRQ4 IOR (READ RECEIVER BUFFER REGISTER) SERIAL OUT (SOUT) THRS IRQ3 or IRQ4 THR IOW (WRITE THR) IOR (READ TIR) W83877ATF/W83877ATG Receiver Timing STAR DATA BITS (5-8) Transmitter Timing STAR DATA (5-8) PARITY THR TSI - 175 - PARITY STOP ...
Page 183
... Modem Control Timing IOW (WRITE MCR) RTS,DTR │ CTS,DSR │ DCD │ → ← │ IRQ3 or IRQ4 IOR (READ MSR) RI ACK IRQ7 W83877ATF/W83877ATG MODEM Control Timing │ │ │ → ← TMWO │ │ │ │ │ ? │ │ → │ ...
Page 184
... Parallel Port Parallel Port Timing IOW INIT, STROBE AUTOFD, SLCTIN PD<0:7> ACK IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP) IRQ W83877ATF/W83877ATG Publication Release Date:November 2006 - 177 - Version 1.0 ...
Page 185
... EPP Data or Address Read Cycle (EPP Version 1.9) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 PD<0:7> t22 t23 t24 ADDRSTB DATASTB WAIT W83877ATF/W83877ATG t18 t17 t21 t25 t27 t26 - 178 - t15 t19 t20 t28 ...
Page 186
... EPP Data or Address Write Cycle (EPP Version 1.9) A10-A0 SD<0:7> t1 IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT t22 PBDIR W83877ATF/W83877ATG t10 t11 t13 t15 t16 t17 t18 t19 t20 Publication Release Date:November 2006 - 179 - t12 t14 t21 Version 1.0 ...
Page 187
... EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t22 t23 ADDRSTB t24 DATASTB WAIT W83877ATF/W83877ATG t18 t21 t25 t26 t27 - 180 - t15 t19 t20 t28 ...
Page 188
... EPP Data or Address Write Cycle (EPP Version 1.7) A10-A0 SD<0:7> t1 IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT Parallel Port FIFO Timing PD<0:7> nSTROBE BUSY W83877ATF/W83877ATG t10 t11 t13 t15 t16 t17 t18 t19 t20 t1 t2 >| t6 >| Publication Release Date:November 2006 - 181 - ...
Page 189
... ECP Parallel Port Forward Timing nAUTOFD PD<0:7> nSTROBE BUSY ECP Parallel Port Reverse Timing PD<0:7> nACK nAUTOFD W83877ATF/W83877ATG 182 - ...
Page 190
... PD5 19 6 DCH2/PD4 18 RDD2/PD3 5 17 STEP2/SLIN 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram W83877ATF/W83877ATG JP13 - 183 - JP 13A DCH2 34 33 HEAD2 32 31 RDD2 30 29 WP2 28 27 TRK02 26 25 WE2 24 23 WD2 22 21 STEP2 ...
Page 191
... STEP2/SLIN 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension 2FDD Connection Diagram 14.3 Four FDD Mode W83777ATF DSA DSB MOA MOB W83877ATF/W83877ATG JP13 74LS139 G1 1Y0 A1 1Y1 B1 1Y2 1Y3 2Y0 2Y1 G2 2Y2 2Y3 184 - JP 13A DCH2 34 33 HEAD2 ...
Page 192
... The top marking of W83877ATG inbond W 83877ATG 220AC27039520 1st line: Winbond logo 2nd line: the type number: W83877ATG; G means lead-free package 3rd line: Tracking code 220 : packages made in '02, week assembly house ID; A means ASE, S means SPIL revision; B means version B, C means version C ...
Page 193
... PACKAGE DIMENSIONS W83877ATF (100-pin QFP 100 See Detail F Seating Plane W83877ATF/W83877ATG θ Detail F - 186 - Dimension in inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A 0.130 3.30 A 0.004 0. 0.107 0.112 0.117 2.73 2.85 2. 0.010 0.012 0.016 0.25 0.30 0.40 c 0.006 0.10 ...
Page 194
... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83877ATF/W83877ATG Important Notice Publication Release Date:November 2006 - 187 - ...