W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 57

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.3.2.3. Set0.Reg2 - Interrupt Status Register/UART FIFO Control Register (ISR/UFR)
(1) Interrupt Status Register: (Write Only)
Legacy UART:
Advanced UART:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Advanced
Reset Value
Legacy
UART
UART
Mode
MIR, FIR modes:
Advanced UART/SIR/ASK-IR, Remote IR modes:
MIR, FIR, Remote IR modes:
Advanced UART/SIR/ASK-IR modes:
MIR, FIR modes:
Remote Controller mode:
TMR_I - Timer Interrupt.
Set to 1 when timer counts to 0. This bit will be affected by (1) the timer registers are
defined in Set4.Reg0 and Set4.Reg1, (2) EN_TMR(Enable Timer, in Set4.Reg2.Bit0)
should be set to 1, (3) ENTMR_I (Enable Timer Interrupt, in Set0.Reg1.Bit7) should be set
to 1.
FSF_I - Frame Status FIFO Interrupt.
Set to 1 when Frame Status FIFO is equal to or larger than the threshold level or Frame
Status FIFO time-out occurs. Clear to 0 when Frame Status FIFO is below the threshold
level.
Not used.
TXTH_I - Transmitter Threshold Interrupt.
Set to 1 if the TBR (Transmitter Buffer Register) FIFO is below the threshold level. Clear
to 0 if the TBR (Transmitter Buffer Register) FIFO is below the threshold level.
DMA_I - DMA Interrupt.
Set to 1 if the DMA controller 8237A sends a TC (Terminal Count) to I/O device which
may be a Transmitter TC or a Receiver TC. Clear to 0 when this register is read.
HS_I - Handshake Status Interrupt.
Set to 1 when the Handshake Status Register has a toggle. Clear to 0 when Handshake
Status Register (HSR) is read. Note that in all IR modes including SIR, ASK-IR, MIR, FIR,
and Remote Control, IR are defaulted to inactive except set IR Handshake Status Enable
(IRHS_EN) to 1.
USR_I - UART Status Interrupt.
Set to 1 when overrun, or parity bit, or stop bit, or silent byte detected error in the UART
Status Register (USR) is set to 1. Clear to 0 when USR is read.
FEND_I - Frame End Interrupt.
Set to 1 when (1) a frame has a grace end to be detected where the frame signal is
defined in the physical layer of IrDA version 1.1 (2) abort signal or illegal signal has been
detected during receiving valid data. Clear to 0 when this register is read.
Not used.
Enable
TMR_I
FIFO
B7
0
Same as previous register defined.
Enable
FSF_I
FIFO
B6
0
TXTH_I
B5
0
1
DMA_I
- 50 -
B4
0
0
W83877ATF/W83877ATG
HS_I
IID2
B3
0
FEND_I
USR_I/
IID1
B2
0
TXEMP_I
IID0
B1
1
RXTH_I
B0
IP
0