W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 138

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W83877ATG

Manufacturer Part Number
W83877ATG
Description
Manufacturer
Nuvoton Technology Corporation of America
Datasheet

Specifications of W83877ATG

Lead Free Status / RoHS Status
Supplier Unconfirmed
11.2.32 Configuration Register 28 (CR28)
When the device is in Extended Function mode and EFIR is 28, the CR28 register can be accessed
through EFDR. Default = 43H if CR6 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
URAIQS3-URAIQS0 (Bit 7-bit 4): Allocate interrupt resource for UART A.
URBIQS3-URBIQS0 (Bit 3-bit 0): Allocate interrupt resource for UART B.
11.2.33 Configuration Register 29 (CR29)
When the device is in Extended Function mode and EFIR is 29, the CR29 register can be accessed
through EFDR. Default = 62H if CR6 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
FDCIQS3-FDCIQS0 (Bit 7-bit 4): Allocate interrupt resource for FDC.
IQNIQS3-IQNIQS0 (Bit 3-bit 0): Allocate interrupt resource for IRQIN.
11.2.34
When the device is in Extended Function mode and EFIR is 2AH, the CR2A register can be accessed
through EFDR. This register default value is 00
Configuration Registers (CR2A)
7
7
7
6
6
6
5
5
5
4
4
4
3
16
3
3
. The bit definitions are as follows:
- 131 -
2
2
2
W83877ATF/W83877ATG
1
1
1
0
0
Publication Release Date:November 2006
0
IRRXDRQSL0
IRRXDRQSL1
IRRXDRQSL2
IRRXDRQSL3
IRTXDRQSL0
IRTXDRQSL1
IRTXDRQSL2
IRTXDRQSL3
URBIQS0
URBIQS1
URBIQS2
URBIQS3
URAIQS0
URAIQS1
URAIQS2
URAIQS3
IQNIQS0
IQNIQS1
IQNIQS2
IQNIQS3
FDCIQS0
FDCIQS1
FDCIQS2
FDCIQS3
Version 1.0

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