W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 150

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

11.2.48
When the device is in Extended Function mode and EFIR is 3AH, the CR3A register can be accessed
through EFDR. The bit definitions are as follows:
Bit 7 - bit 6 : Reserved, fixed at 0.
TMIN_SEL (Bit 5): Time resolution of the auto power machines of all devices.
CR35 to CR39 store the initial counts of the devices.
Bit 4 - bit 2: Reserved, fixed at 0.
SMI_EN (Bit 2): SMI output pin enable.
While an SMI event is raised on the output of the SMI logic, this bit determines whether the SMI
interrupt is generated on the SMI output SMI pin and on the Serial IRQ IRQSER pin while in Serial
IRQ mode.
Bit 1:Reserved.
UPULLEN (Bit 0): Enable the pull up of IRQSER pin in Serial IRQ mode.
11.2.49
Reserved for testing. Should be kept all 0's.
11.2.50
When the device is in Extended Function mode and EFIR is 40H, the CR40 register can be accessed
through EFDR. The bit definitions are as follows:
0
1
0
1
0
1
Configuration Register 3A (CR3A), default=00H
Configuration Register 3B (CR3B), default=00H
Configuration Register 40 (CR40), default=00H
one second
one miniute
disable
enable
disable the pull up of IRQSER pin.
enable the pull up of IRQSER pin.
7
6
5
4
3
- 143 -
2
W83877ATF/W83877ATG
1
0
Publication Release Date:November 2006
UPULLEN
reserved
SMI_EN
reserved
reserved
TMIN_SEL
reserved
reserved
Version 1.0