W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 94

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

7.3.1
Note : The base addresses are specified by CR23, which are determined by configuration register or hardware setting.
Note: The mode selection bits are bit 7-5 of the Extended Control Register.
7.3.2
Modes 000 (SPP) and 001 (PS/2) (Data Port)
During a write operation, the Data Register latches the contents of the data bus on the rising edge of
the input. The contents of this register are output to the PD0-PD7 ports. During a read operation, ports
PD0-PD7 are read and output to the host. The bit definitions are as follows:
MODE
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
000
001
010
011
100
101
110
111
NAME
ECP Register and Mode Definitions
Data and ecpAFifo Port
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
ECP Parallel Port mode
EPP mode (If this option is enabled in the CR9 and CR0 to select ECP/EPP mode)
Reserved
Test mode
Configuration mode
Base+000h
Base+000h
Base+001h
Base+002h
Base+400h
Base+400h
Base+400h
Base+400h
Base+401h
Base+402h
ADDRESS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I/O
R
R
ECP MODES
DESCRIPTION
- 87 -
000-001
011
010
011
110
111
111
All
All
All
W83877ATF/W83877ATG
Publication Release Date:November 2006
Data Register
ECP FIFO (Address)
Status Register
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
Control Register
FUNCTION
Version 1.0