W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 126

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

11.2.20
When the device is in Extended Function mode and EFIR is 14H, the CR14 register can be accessed
through EFDR. The bit definitions are as follows:
GIOP0MD2-GIOP0MD0 (Bit 7-bit 5): GIOP0 pin mode selection
GIO0CSH(Bit 4):
GCS0IOR (Bit 3): See below.
GIOP0MD2
0
1
0
0
0
0
1
Configuration Register 14 (CR14), default = 00H
the Chip Select pin will be active LOW when (AEN = L) AND (SA10-0 = GIO0AD10-
0) OR (NIOR = L) OR (NIOW = L)
the Chip Select pin will be active HIGH when (AEN = L) AND (SA10-0 =
GIO0AD10-0) OR (NIOR = L) OR (NIOW = L)
GIOP0MD1
X
0
0
1
1
7
GIOP0MD0
6
X
0
1
0
1
5
4
inactive (tri-state)
as a data output pin (SD0 → GIOP0), when (AEN = L)
AND (NIOW = L) AND (SA10-0 = GIO0AD10-0), the
value of SD0 will be present on GIOP0
as a data input pin (GIOP0 → SD0), when (AEN = L)
AND (NIOR = L) AND (SA10-0 = GIO0AD10-0), the
value of GIOP0 will be present on SD0
as a data input/output pin (GIOP0 ↔ SD0).
When (AEN = L) AND (NIOW = L) AND (SA10-0 =
GIO0AD10-0), the value of SD0 will be present on
GIOP0 When (AEN = L) AND (NIOR = L) AND (SA10-0
= GIO0AD10-0), the value of GIOP0 will be present on
SD0
as a Chip Select pin, the pin will be active at (AEN =
L) AND (SA10-0 = GIO0AD10-0) OR (NIOR = L) OR
(NIOW = L)
3
- 119 -
2
W83877ATF/W83877ATG
1
0
Publication Release Date:November 2006
GDA0IPI
GDA0OPI
GCS0IOW
GCS0IOR
GIO0CSH
GIOP0MD0
GIOP0MD1
GIOP0MD2
GIOP0 pin
Version 1.0