W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 154

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

11.2.55
When the device is in Extended Function mode and EFIR is 45H, the CR45 register can be accessed
through EFDR. The bit definitions are as follows:
Bit 7 - bit 4 : Reserved, fixed at 0.
Bit 3 - bit 0 : Enable bits of the SMI generation due to the device's IRQ.
These bits enable the generation of an SMI interrupt due to any IRQ of the devices respectively.
These 4 bits control the printer port, FDC, UART A, and UART B SMI logics individually. The SMI logic
output for the IRQs is as follows:
SMI logic output = (URBIRQEN and URBIRQSTS) or (URAIRQEN and URAIRQSTS)
(FDCIRQEN and FDCIRQSTS) or (PRTIRQEN and PRTIRQSTS)
If any device's IRQ is raised, the coresponding IRQ status bit in CR42 is set. If the device's enable bit
is set and SMI_EN(in CR3A) and CHIPPME(in CR32) is both set, then SMI interrupt occurs on the
SMI output pin.
PRTIRQEN (Bit 3):
FDCIRQEN (Bit 2):
URAIRQEN (Bit 1):
URBIRQEN (Bit 0):
0
1
0
1
0
1
0
1
Configuration Register 45 (CR45), default=00H
disable the generation of an SMI interrput due to the printer port's IRQ.
enable the generation of an SMI interrput due to the printer port's IRQ.
disable the generation of an SMI interrupt due to the FDC's IRQ.
enable the generation of an SMI interrupt due to the FDC's IRQ.
disable the generation of an SMI interrupt due to the UART A's IRQ.
enable the generation of an SMI interrupt due to the UART A's IRQ.
disable the generation of an SMI interrupt due to the UART B's IRQ.
enable the generation of an SMI interrupt due to the UART B's IRQ.
7
6
5
4
3
- 147 -
2
W83877ATF/W83877ATG
1
0
Publication Release Date:November 2006
URBIRQEN
URAIRQEN
FDCIRQEN
PRTIRQEN
reserved
reserved
reserved
reserved
Version 1.0
or