W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 73

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.3.7.4. Set5.Reg4 - Infrared Config Register 1 (IRCFG1)
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3~2:
Bit 1:
Bit 0:
6.3.7.5. Set5.Reg5 - Frame Status FIFO Register (FS_FO)
This register are indicated the FIFO bottom of frame status.
Reset Value
Reset Value
IRCFG1
FS_FO
REG.
REG.
FSF_TH
Reserved , write 0.
FSF_TH - Frame Status FIFO Threshold
Set this bit to determine the frame status FIFO threshold level and to generate the FSF_I.
The threshold level values are defined as follows.
FEND_MD - Frame End mode
Write to 1 enables hardware automatically to split same length frame defined Set4. Reg4
and Set4.Reg5, i.e., TFRLL/TFRLH.
AUX_RX - Auxiliary Receiver Pin
Write to 1 selects IRRX input pin. (Refer to Set7.Reg7.Bit5)
Reserved , write 0.
IRHSSL - Infrared Handshake Status Select
Write to 0 brings the HSR (Handshake Status Register) into normal operation the same
as UART. Write to 1 disables HSR; reading HSR will then return 30
IR_FULL - Infrared Full Duplex Operation
Write to 0 will cause IR function to operate in half duplex. Write to 1 will cause IR function
to operate in full duplex.
FSFDR
BIT 7
BIT 7
0
1
0
0
-
FSF_TH
LST_FR
BIT 6
BIT 6
0
0
FEND_M AUX_RX
BIT 5
BIT 5
0
0
-
MX_LEX PHY_ERR CRC_ERR RX_OV
BIT 4
BIT 4
- 66 -
STATUS FIFO THRESHOLD LEVEL
0
0
W83877ATF/W83877ATG
BIT 3
BIT 3
0
0
-
2
4
BIT 2
BIT 2
0
0
-
16
.
IRHSSL
BIT 1
BIT 1
0
0
IR_FULL
FSF_OV
BIT 0
BIT 0
0
0